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| INTEGRATED CIRCUITS DATA SHEET SAA55xx TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Preliminary specification Supersedes data of 1999 Aug 02 File under Integrated Circuits, IC02 2000 Feb 23 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) CONTENTS 1 2 3 4 5 6 6.1 6.2 7 7.1 8 8.1 8.2 8.3 8.4 8.5 8.6 9 9.1 9.2 9.3 10 10.1 10.2 10.3 10.4 11 11.1 11.2 11.3 11.4 12 13 13.1 14 14.1 14.2 14.3 14.4 15 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION Pinning Pin description MICROCONTROLLER Microcontroller features MEMORY ORGANIZATION ROM bank switching RAM organisation Data memory SFR memory Character set feature bits External (auxiliary) memory REDUCED POWER MODES Idle mode Power-down mode Standby mode I/O FACILITY I/O ports Port type Port alternative functions LED support INTERRUPT SYSTEM Interrupt enable structure Interrupt enable priority Interrupt vector address Level/edge interrupt TIMER/COUNTER WATCHDOG TIMER Watchdog Timer operation PULSE WIDTH MODULATORS PWM control Tuning Pulse Width Modulator (TPWM) TPWM control Software ADC (SAD) I2C-BUS SERIAL I/O 15.1 16 16.1 16.2 16.3 16.4 17 17.1 18 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 18.11 18.12 18.13 18.14 18.15 19 20 21 22 23 24 25 26 26.1 26.2 26.3 26.4 27 28 29 I2C-bus port selection MEMORY INTERFACE Memory structure Memory mapping Addressing memory Page clearing DATA CAPTURE Data Capture features DISPLAY SAA55xx Display features Display modes Display feature descriptions Character and attribute coding Screen and global controls Text display controls Display positioning Character set ROM addressing Redefinable characters Display synchronization Video/Data switch (Fast Blanking) polarity Video/data switch adjustment RGB brightness control Contrast reduction MEMORY MAPPED REGISTERS (MMR) LIMITING VALUES CHARACTERISTICS QUALITY AND RELIABILITY APPLICATION INFORMATION ELECTROMAGNETIC COMPATIBILITY (EMC) GUIDELINES PACKAGE OUTLINES SOLDERING Introduction to soldering through-hole mount packages Soldering by dipping or by solder wave Manual soldering Suitability of through-hole mount IC packages for dipping and wave soldering methods DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS 2000 Feb 23 2 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 1 FEATURES SAA55xx * Single-chip microcontroller with integrated On-Screen Display (OSD) * One Time Programmable (OTP) memory for both Program ROM and character sets * Single power supply: 3.0 to 3.6 V * 5 V tolerant digital inputs and I/O * 29 I/O port via individual addressable controls * Programmable I/O for push-pull, open-drain and quasi-bidirectional * Two port lines with 8 mA sink (at <0.4 V) capability, for direct drive of Light Emitting Diode (LED) * Single crystal oscillator for microcontroller, OSD and data capture * Power reduction modes: Standby, Idle and Power-down * Byte level I2C-bus up to 200 kHz with dual port I/O (Slave mode up to 400 kHz) * 32 Dynamically Redefinable Characters for OSDs * Special graphic characters allowing four colours per character * Selectable character height 9, 10, 13 and 16 TV lines * Pin compatibility throughout family * Operating temperature: -20 to +70C. 2 GENERAL DESCRIPTION The SAA55xx OSD only family of devices are a derivative of the Philips industry standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system, On-Screen Display (OSD) and some versions include an integrated data capture function. The main differences between the OSD only family and the SAA55xx Text/CC family of baseline devices are: * Program ROM size: 16 to 64-kbyte * Display RAM size: 1.25-kbyte (1 page Text OSD or CC/OSD) * Auxiliary RAM size: 0.75-kbyte * No teletext data capture (Closed Caption only) * Additional power saving mode (Standby). 2000 Feb 23 3 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 3 QUICK REFERENCE DATA SYMBOL Supply VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDC(stb) IDDA IDDA(id) IDDA(pd) IDDA(stb) fxtal Tamb Tstg Note 1. Peripheral supply current is dependent on external components and voltage levels on I/Os. 4 ORDERING INFORMATION TYPE NUMBER(1) NAME SAA5540PS/nnnn SAA5541PS/nnnn SAA5542PS/nnnn SAA5543PS/nnnn SAA5547PS/nnnn Notes 1. `nnnn' is a four digit number uniquely referencing the microcontroller program mask. 2. For details of the LQFP100 package, please contact your local regional sales office for availability. SDIP52 PACKAGE(2) ROM DESCRIPTION plastic shrink dual in-line package; 52 leads (600 mil) VERSION SOT247-1 16-kbyte 32-kbyte 48-kbyte 64-kbyte 24-kbyte any supply voltage (VDD to VSS) periphery supply current; note 1 core supply current Idle mode core supply current Power-down mode core supply current Standby mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current Standby mode analog supply current Fundamental mode nominal frequency operating ambient temperature storage temperature 3.0 1 - - - - - - - - - -20 -55 3.3 - 12 383 666 5.1 45 444 433 809 12 - - 3.6 - 18 600 900 9 48 700 700 950 - +70 +125 PARAMETER MIN. TYP. SAA55xx MAX. UNIT V mA mA A A mA mA A A A MHz C C RAM 256-byte 512-byte 750-byte 750-byte 750-byte yes yes yes yes yes CC 2000 Feb 23 4 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 5 BLOCK DIAGRAM SAA55xx handbook, full pagewidth I2C-bus, general I/O TV CONTROL AND INTERFACE ROM (16 TO 64-KBYTE) MICROPROCESSOR (80C51) SRAM (256-BYTE) DRAM (UP TO 2-KBYTE) MEMORY INTERFACE R CVBS DATA CAPTURE DISPLAY G B VDS CVBS DATA CAPTURE TIMING DISPLAY TIMING GSA005 VSYNC HSYNC Fig.1 Block diagram (top level architecture). 2000 Feb 23 5 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 6 6.1 PINNING INFORMATION Pinning SAA55xx handbook, halfpage P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 1 2 3 4 5 6 7 8 9 52 P1.5/SDA1 51 P1.4/SCL1 50 P1.7/SDA0 49 P1.6/SCL0 48 P1.3/T1 47 P1.2/INT0 46 P1.1/T0 45 P1.0/INT1 44 VDDP 43 RESET 42 XTALOUT 41 XTALIN 40 OSCGND P3.1/ADC1 10 P3.2/ADC2 11 P3.3/ADC3 12 VSSC 13 P0.0 14 P0.1 15 P0.2 16 P0.3 17 P0.4 18 P0.5 19 P0.6 20 P0.7 21 VSSA 22 CVBS0 23 CVBS1 24 SYNC_FILTER 25 IREF 26 MBK951 SAA55xx 39 VDDC 38 VSSP 37 VSYNC 36 HSYNC 35 VDS 34 R 33 G 32 B 31 VDDA 30 P3.4/PWM7 29 COR 28 VPE 27 FRAME Fig.2 SDIP52 pin configuration. 2000 Feb 23 6 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx 100 P2.0/TPWM 98 P2.6/PWM5 97 P2.5/PWM4 96 P2.4/PWM3 95 P2.3/PWM2 94 P2.2/PWM1 93 P2.1/PWM0 84 P1.5/SDA1 82 P1.7/SDA0 83 P1.4/SCL1 81 P1.6/SCL0 79 P1.2/INT0 handbook, full pagewidth P2.7/PWM6 P3.0/ADC0 n.c. P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 n.c. n.c. n.c. 1 2 3 4 5 6 7 8 9 76 P1.0/INT1 75 VDDP 74 n.c. 73 RESET 72 n.c. 71 XTALOUT 70 XTALIN 69 OSCGND 68 n.c. 67 n.c. 66 n.c. 65 n.c. 64 n.c. 63 VDDC 62 VPE_2 61 n.c. 60 VSSP 59 P3.6 58 n.c. 57 n.c. 56 n.c. 55 VSYNC 54 P3.5 53 HSYNC 52 VDS 51 n.c. n.c. 50 GSA001 80 P1.3/T1 78 P1.1/T0 R 48 99 n.c. 92 n.c. 91 n.c. 90 n.c. 89 n.c. 88 n.c. 87 n.c. 86 n.c. 85 n.c. n.c. 10 VSSC 11 VSSP 12 P0.5 13 n.c. 14 n.c. 15 P0.0 16 P0.1 17 P0.2 18 n.c. 19 n.c. 20 n.c. 21 P0.3 22 n.c. 23 P0.4 24 P3.7 25 n.c. 26 n.c. 27 P0.6 28 P0.7 29 VSSA 30 CVBS0 31 CVBS1 32 n.c. 33 SYNC_FILTER 34 IREF 35 n.c. 36 n.c. 37 n.c. 38 n.c. 39 n.c. 40 FRAME 41 VPE 42 COR 43 P3.4/PWM7 44 VDDA 45 B 46 G 47 n.c. 49 SAA55xx Fig.3 LQFP100 pin configuration. 2000 Feb 23 7 77 n.c. Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 6.2 Pin description SDIP52 and LQFP100 packages PIN SYMBOL SDIP52 P2.0/TPWM P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 P3.4/PWM7 P3.5 P3.6 P3.7 VSSC P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 VSSA CVBS0 CVBS1 SYNC_FILTER IREF FRAME 1 2 3 4 5 6 7 8 9 10 11 12 30 - - - 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 LQFP100 100 93 94 95 96 97 98 1 2 4 5 6 44 54 59 25 11 16 17 18 22 24 13 28 29 30 31 32 34 35 41 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O - I I I I O analog ground core ground TYPE DESCRIPTION SAA55xx Table 1 Port 2. 8-bit programmable bidirectional port with alternative functions. P2.0/TPWM is the output for the 14-bit high precision PWM. P2.1/PWM0 to P2.7/PWM6 are the outputs for the 6-bit PWMs 0 to 6. Port 3. 8-bit programmable bidirectional port with alternative functions. P3.0/ADC0 to P3.3/ADC3 are the inputs for the software ADC facility. P3.4/PWM7 is the output for the 6-bit PWM7. P3.5 to P3.7 have no alternative functions and are only available with the LQFP100 package. Port 0. 8-bit programmable bidirectional port. P0.5 and P0.6 have 8 mA current sinking capability for direct drive of LEDs. Composite Video Baseband Signal (CVBS) input. A positive-going 1 V (peak-to-peak) input is required. Connected via a 100 nF capacitor. CVBS sync filter input. This pin should be connected to VSSA via a 100 nF capacitor. Reference current input for analog circuits, connected to VSSA via a 24 K resistor. De-interlace output synchronised with the VSYNC pulse to produce a non-interlaced display by adjustment of the vertical deflection circuits. OTP programming voltage VPE 28 42 I 2000 Feb 23 8 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) PIN SYMBOL SDIP52 COR 29 LQFP100 43 O TYPE DESCRIPTION SAA55xx Open-drain, active LOW output which allows selective contrast reduction of the TV picture to enhance a mixed mode display. +3.3 V analog power supply Pixel rate output of the BLUE colour information. Pixel rate output of the GREEN colour information. Pixel rate output of the RED colour information. Video/data switch push-pull output for dot rate fast blanking. Schmitt triggered input TTL version of the horizontal sync pulse. The polarity of this pulse is programmable by register bit TXT1.H POLARITY. Schmitt triggered input for a TTL version of the vertical sync pulse. The polarity of this pulse is programmable by register bit TXT1.V POLARITY. periphery ground +3.3 V core power supply crystal oscillator ground 12 MHz crystal oscillator input 12 MHz crystal oscillator output If the reset input is HIGH for at least 2 machine cycles (24 oscillator periods) while the oscillator is running, the device is reset. This pin should be connected to VDDP via a capacitor. +3.3 V periphery power supply Port 1. 8-bit programmable bidirectional port with alternative functions. P1.0/INT1 is external interrupt 1 which can be triggered on the rising and falling edge of the pulse. P1.1/T0 is the Counter/Timer 0. P1.2/INT0 is external interrupt 0. P1.3/T1 is the Counter/Timer 1. P1.6/SCL0 is the serial clock input for the I2C-bus and P1.7/SDA0 is the serial data port for the I2C-bus. P1.4/SCL1 is the serial clock input for the I2C-bus and P1.5/SDA1 is the serial data port for the I2C-bus. OTP programming voltage not connected VDDA B G R VDS HSYNC 31 32 33 34 35 36 45 46 47 48 52 53 - O O O O I VSYNC 37 55 I VSSP VDDC OSCGND XTALIN XTALOUT RESET 38 39 40 41 42 43 12, 60 63 69 70 71 73 - - - I O I VDDP P1.0/INT1 P1.1/T0 P1.2/INT0 P1.3/T1 P1.6/SCL0 P1.7/SDA0 P1.4/SCL1 P1.5/SDA1 VPE_2 n.c. 44 45 46 47 48 49 50 51 52 - - 75 76 78 79 80 81 82 83 84 62 3, 7 to 10, 14, 15, 19 to 21, 23, 26, 27, 33, 36 to 40, 49 to 51, 56 to 58, 61, 64 to 68, 72, 74, 77, 85 to 92, 99 - I/O I/O I/O I/O I/O I/O I/O I/O I - 2000 Feb 23 9 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 7 MICROCONTROLLER 8 MEMORY ORGANIZATION SAA55xx The functionality of the microcontroller used on this device is described here with reference to the industry standard 80C51 microcontroller. A full description of its functionality can be found in the "Handbook IC20, 80C51-Based 8-bit Microcontrollers". 7.1 Microcontroller features The device has the capability of a maximum of 64-kbyte Program ROM and 2-kbyte Data RAM internally. 8.1 ROM bank switching As the Program ROM does not exceed 64 kbytes in any of the OSD only variants, ROM bank switching is not required. The memory and security bits are structured as shown in Fig.4. The OSD only security bits are set as shown in Fig.5 for production programmed devices. The OSD only security bits are set as shown in Fig.6 for production blank devices. 8.2 RAM organisation * 80C51 microcontroller core standard instruction set and timing * 1 s machine cycle * Maximum 64K x 8-bit program ROM * 2 x 8-bit auxiliary RAM, maximum of 1.25 kbytes required for display * Interrupt controller for individual enable/disable with two level priority * Two 16-bit timer/counter registers * Watchdog Timer * Auxiliary RAM page pointer * 16-bit data pointer * Standby, Idle and Power-down modes * 29 general I/O lines * Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals * One 14-bit PWM for Voltage Synthesis Tuner (VST) control * 8-bit Analog-to-Digital Converter (ADC) with four multiplexed inputs * 2 high current outputs for directly driving LEDs * I2C-bus byte level bus interface with dual ports. The Internal Data RAM is organized into two areas, Data memory and Special Function Registers (SFRs). 8.3 Data memory The Data memory is 256 x 8-bit, and occupies the address range 00H to FFH when using indirect addressing and 00H to 7FH when using direct addressing. The SFRs occupy the address range 80H to FFH and are accessible using direct addressing only. The lower 128 bytes of Data memory are mapped as shown in Fig.8. The lowest 24 bytes are grouped into 4 banks of 8 registers, the next 16 bytes above the register banks form a block of bit addressable memory space. The upper 128 bytes are not allocated for any special area or functions. 2000 Feb 23 10 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth MEMORY SECURITY BITS INTERACTION USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) PROGRAM ROM USER ROM (64K x 8-BIT) CHARACTER ROM USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) USER ROM (9K x 12-BIT) GSA006 Fig.4 Memory and security bit structures. handbook, full pagewidth MEMORY SECURITY BITS SET USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED PROGRAM ROM DISABLED CHARACTER ROM DISABLED ENABLED GSA007 Fig.5 Security bits for production devices. 2000 Feb 23 11 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth MEMORY SECURITY BITS SET USER ROM PROGRAMMING (ENABLE/DISABLE) VERIFY (ENABLE/DISABLE) ENABLED PROGRAM ROM ENABLED CHARACTER ROM ENABLED ENABLED GSA008 Fig.6 Security bits for production blank devices. handbook, halfpage DATA MEMORY SPECIAL FUNCTION REGISTERS FFH upper 128 bytes 80H 7FH lower 128 bytes 00H accessible by direct and indirect addressing MBK956 accessible by indirect addressing only accessible by direct addressing only Fig.7 Internal data memory. 2000 Feb 23 12 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, halfpage 7FH 30H 2FH bit-addressable space (bit addresses 00H to 7FH) 20H 1FH 18H 17H 10H 0FH 08H 07H 0 4 banks of 8 registers (R0 to R7) R7 R0 R7 R0 R7 R0 R7 R0 MGM677 Fig.8 Lower 128 bytes of internal RAM. 2000 Feb 23 13 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 8.4 SFR memory 2000 Feb 23 14 Philips Semiconductors TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) The Special Function Register (SFR) space is used for port latches, timer, peripheral control, acquisition control, display control, etc. These registers can only be accessed by direct addressing. Sixteen of the addresses in the SFR space are both bit and byte addressable. The bit addressable SFRs are those whose address ends in 0H or 8H. A summary of the SFR map in address order is shown in Table 2. A description of each of the SFR bits is shown in Table 3 which presents the SFRs in alphabetical order. Table 2 SFR memory map NAME PO SP DPL DPH PCON TCON TMOD TL0 TL1 TH0 TH1 P1 P0CFGA P0CFGB SADB P1CFGA P1CFGB P2 P2CFGA P2CFGB IE P3 TXT18 TXT19 TXT20 7 P07 SP7 DPL7 DPH7 0 TF1 GATE TL07 TL17 TH07 TH17 P17 P0CFGA7 P0CFGB7 0 P1CFGA7 P1CFGB7 P27 P2CFGA7 P2CFGB7 EA P37 NOT3 TEN DRCS ENABLE 6 P06 SP6 DPL6 DPH6 ARD TR1 C/T TL06 TL16 TH06 TH16 P16 P0CFGA6 P0CFGB6 0 P1CFGA6 P1CFGB6 P26 P2CFGA6 P2CFGB6 EBUSY P36 NOT2 TC2 OSD PLANES 5 P05 SP5 DPL5 DPH5 RFI TF0 M1 TL05 TL15 TH05 TH15 P15 P0CFGA5 P0CFGB5 0 P1CFGA5 P1CFGB5 P25 P2CFGA5 P2CFGB5 ES2 P35 NOT1 TC1 0 4 P04 SP4 DPL4 DPH4 WLE TR0 M0 TL04 TL14 TH04 TH14 P14 P0CFGA4 P0CFGB4 DC_COMP P1CFGA4 P1CFGB4 P24 P2CFGA4 P2CFGB4 ECC P34 NOT0 TC0 0 3 P03 SP3 DPL3 DPH3 GF1 IE1 GATE TL03 TL13 TH03 TH13 P13 P0CFGA3 P0CFGB3 SAD3 P1CFGA3 P1CFGB3 P23 P2CFGA3 P2CFGB3 ET1 P33 0 0 OSD LANG ENABLE 2 P02 SP2 DPL2 DPH2 GF0 IT1 C/T TL02 TL12 TH02 TH12 P12 P0CFGA2 P0CFGB2 SAD2 P1CFGA2 P1CFGB2 P22 P2CFGA2 P2CFGB2 EX1 P32 0 0 OSD LAN2 1 P01 SP1 DPL1 DPH1 PD IE0 M1 TL01 TL11 TH01 TH11 P11 P0CFGA1 P0CFGB1 SAD1 P1CFGA1 P1CFGB1 P21 P2CFGA1 P2CFGB1 ET0 P31 BS1 TS1 OSD LAN1 0 P00 SP0 DPL0 DPH0 IDL IT0 M0 TL00 TL10 TH00 TH10 P10 P0CFGA0 P0CFGB0 SAD0 P1CFGA0 P1CFGB0 P20 P2CFGA0 P2CFGB0 EX0 P30 BS0 TS0 OSD LAN0 RESET FFH 07H 00H 00H 00H 00H 00H 00H 00H 00H 00H FFH FFH 00H 00H FFH 00H FFH FFH ADD R/W 80H 81H 82H 83H 87H 88H 89H R/W R/W R/W R/W R/W R/W R/W 8AH R/W 8BH R/W 8CH R/W 8DH R/W 90H 96H 97H 98H 9FH R/W R/W R/W R/W R/W 9EH R/W A0H R/W A6H R/W A7H R/W A8H R/W B0H R/W B2H R/W B3H R/W B4H R/W Preliminary specification 00H 00H SAA55xx FFH 00H 00H 00H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Feb 23 15 Philips Semiconductors ADD R/W B5H R/W B6H R B7H R/W B8H R/W B9H R/W BEH R/W BFH R/W C0H R/W C1H R/W C4H R/W NAME TXT21 TXT22 CCLIN IP TXT17 P3CFGA P3CFGB TXT0 TXT1 TXT4 7 DISP LINES1 GPF7 0 0 0 P3CFGA7 P3CFGB7 (reserved) 0 (reserved) 0 OSD BANK ENABLE BKGND OUT BKGND OUT (reserved) 0 (reserved) 0 CURSOR FREEZE 0 D7 525/625 SYNC C TD7 TPWE 6 DISP LINES0 GPF6 0 PBUSY FORCE ACQ1 P3CFGA6 P3CFGB6 (reserved) 0 (reserved) 0 QUAD WIDTH ENABLE BKGND IN BKGND IN CURSOR ON FLICKER STOP ON CLEAR MEMORY 0 D6 ROM VER4 5 CHAR SIZE1 GPF5 0 PES2 FORCE ACQ0 P3CFGA5 P3CFGB5 AUTO FRAME (reserved) 0 EAST/WEST 4 CHAR SIZE0 GPF4 CS4 PCC FORCE DISP1 P3CFGA4 P3CFGB4 (reserved) 0 (reserved) 0 DISABLE DOUBLE HEIGHT COR IN COR IN (reserved)0 DISABLE SPANISH R4 C4 D4 I2C 3 PORT 1 2 CC ON GPF2 CS2 PX1 SCREEN COL2 P3CFGA2 P3CFGB2 DISABLE FRAME FIELD POLARITY C MESH ENABLE TEXT IN TEXT IN BOX ON 24 WSS RECEIVED R2 C2 D2 I2C 1 PORT 0 0 CC/TXT GPF0 CS0 PX0 SCREEN COL0 P3CFGA0 P3CFGB0 (reserved) 0 V POLARITY SHADOW ENABLE PICTURE ON IN PICTURE ON IN BOX ON 0 CVBS1/ CVBS0 R0 C0 D0 VIDEO SIGNAL QUALITY P TD0 TD8 RESET 02H XXH 15H 00H 00H FFH 00H 00H 00H 00H TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) GPF3 CS3 PT1 FORCE DISP0 P3CFGA3 P3CFGB3 (reserved) 0 (reserved) 0 B MESH ENABLE TEXT OUT TEXT OUT DOUBLE HEIGHT PKT 26 RECEIVED R3 C3 D3 GPF1 CS1 PT0 SCREEN COL1 P3CFGA1 P3CFGB1 (reserved) 0 H POLARITY TRANS ENABLE PICTURE ON OUT PICTURE ON OUT BOX ON 1 - 23 WSS ON R1 C1 D1 1 C5H R/W C6H R/W C7H R/W C8H R/W C9H R/W CAH R/W CBH R/W CCH R TXT5 TXT6 TXT7 TXT8 TXT9 TXT10 TXT11 TXT12 COR OUT COR OUT (reserved) 0 (reserved) 0 (reserved) 0 C5 D5 ROM VER3 03H 03H 00H 00H 00H 00H 00H XXXX XX1X Preliminary specification ROM VER2 ROM VER1 ROM VER0 SAA55xx D0H R/W D2H R/W D3H R/W PSW TDACL TDACH AC TD6 1 F0 TD5 TD13 RS1 TD4 TD12 RS0 TD3 TD11 OV TD2 TD10 - TD1 TD9 00H 00H 40H This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Feb 23 16 Philips Semiconductors ADD R/W D4H R/W D5H R/W D6H R/W D7H R D8H R/W D9H R DAH R/W DBH R/W DCH R/W DDH R/W DEH R/W DFH R/W E0H R/W E4H R/W E7H R E8H R/W F0H F8H FAH R/W R/W R/W NAME PWM7 PWM0 PWM1 CCDAT1 S1CON S1STA S1DAT S1ADR PWM3 PWM4 PWM5 PWM6 ACC PWM2 CCDAT2 SAD B TXT13 XRAMP ROMBK WDTKEY WDT 7 PW7E PW0E PW1E CCD17 CR2 STAT4 DAT7 ADR6 PW3E PW4E PW5E PW6E ACC7 PW2E CCD27 VHI B7 (reserved) 0 XRAMP7 STANDBY WKEY7 WDV7 6 1 1 1 CCD16 ENSI STAT3 DAT6 ADR5 1 1 1 1 ACC6 1 CCD26 CH1 B6 PAGE CLEARING XRAMP6 0 WKEY6 WDV6 5 PW7V5 PW0V5 PW1V5 CCD15 STA STAT2 DAT5 ADR4 PW3V5 PW4V5 PW5V5 PW6V5 ACC5 PW2V5 CCD25 CH0 B5 525 DISPLAY XRAMP5 0 WKEY5 WDV5 4 PW7V4 PW0V4 PW1V4 CCD14 STO STAT1 DAT4 ADR3 PW3V4 PW4V4 PW5V4 PW6V4 ACC4 PW2V4 CCD24 ST B4 (reserved) 0 XRAMP4 0 WKEY4 WDV4 3 PW7V3 PW0V3 PW1V3 CCD13 SI STAT0 DAT3 ADR2 PW3V3 PW4V3 PW5V3 PW6V3 ACC3 PW2V3 CCD23 SAD7 B3 (reserved) 0 XRAMP3 0 WKEY3 WDV3 2 PW7V2 PW0V2 PW1V2 CCD12 AA 0 DAT2 ADR1 PW3V2 PW4V2 PW5V2 PW6V2 ACC2 PW2V2 CCD22 SAD6 B2 (reserved) 0 XRAMP2 0 WKEY2 WDV2 1 PW7V1 PW0V1 PW1V1 CCD11 CR1 0 DAT1 ADR0 PW3V1 PW4V1 PW5V1 PW6V1 ACC1 PW2V1 CCD21 SAD5 B1 (reserved) 0 XRAMP1 (reserved) 0 WKEY1 WDV1 0 PW7V0 PW0V0 PW1V0 CCD10 CR0 0 DAT0 GC PW3V0 PW4V0 PW5V0 PW6V0 ACC0 PW2V0 CCD20 SAD4 B0 (reserved) 0 XRAMP0 (reserved) 0 WKEY0 WDV0 RESET 40H 40H 40H 00H 00H F8H 00H 00H 40H 40H 40H 40H 00H 40H 00H 00H 00H XXXX XXX0 00H 00H 00H 00H TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) FBH R/W FEH W FFH R/W Preliminary specification SAA55xx Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Table 3 SFR bit description BIT Accumulator (ACC) ACC7 to ACC0 B Register (B) B7 to B0 CC data byte 1 (CCDAT1) CCD17 to CCD10 CC data byte 2 (CCDAT2) CCD26 to CCD20 CC line (CCLIN) CS4 to CS0 Data Pointer High byte (DPH) DPH7 to DPH0 Data pointer Low byte (DPL) DPL7 to DPL0 Interrupt Enable Register (IE) EA EBUSY ES2 ECC ET1 EX1 ET0 EX0 Interrupt Priority Register (IP) PBUSY PES2 PCC PT1 PX1 PT0 PX0 Port 0 (P0) P07 to P00 Port 0 I/O register connected to external pins priority EBUSY interrupt priority ES2 Interrupt priority ECC interrupt priority Timer 1 interrupt priority external interrupt 1 priority Timer 0 interrupt priority external interrupt 0 closed caption slice line using 525-line number closed caption second data byte closed caption first data byte B register value accumulator value FUNCTION SAA55xx data pointer high byte, used with DPL to address auxiliary memory data pointer low byte, used with DPH to address auxiliary memory disable all interrupts (logic 0), or use individual interrupt enable bits (logic 1) enable BUSY interrupt enable I2C-bus interrupt enable closed caption interrupt enable Timer 1 interrupt enable external interrupt 1 enable Timer 0 interrupt enable external interrupt 0 2000 Feb 23 17 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT Port 1 (P1) P17 to P10 Port 2 (P2) P27 to P20 Port 3 (P3) P37 to P30 Port 2 I/O register connected to external pins Port 1 I/O register connected to external pins FUNCTION SAA55xx Port 3 I/O register connected to external pins; P37 to P35 are only available with the LQFP100 package Port 0 Configuration A (P0CFGA) and Port 0 Configuration B (P0CFGB) P0CFGA<7:0> and P0CFGB<7:0> These two registers are used to configure Port 0 pins. For example, the I/O configuration of Port 0 pin 3 is controlled using bit 3 in both P0CFGA and P0CFGB. P0CFGB 2000 Feb 23 18 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT Power Control Register (PCON) ARD RFI WLE GF1 GF0 PD IDL Program Status Word (PSW) C AC F0 RS1 to RS0 carry bit auxiliary carry bit flag 0, general purpose flag register bank selector bits; RS<1:0>: 00 = Bank 0 (00H to 07H) 01 = Bank 1 (08H to 0FH) 10 = Bank 2 (10H to 17H) 11 = Bank 3 (18H to 1FH) OV P overflow flag parity bit FUNCTION SAA55xx auxiliary RAM disable, all MOVX instructions access the external data memory disable ALE during internal access to reduce radio frequency interference Watchdog Timer enable general purpose flag general purpose flag Power-down mode activation bit Idle mode activation bit Pulse Width Modulator 0 Control Register (PWM0) PW0E PW0V5 to PW0V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 1 Control Register (PWM1) PW1E PW1V5 to PW1V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 2 Control Register (PWM2) PW2E PW2V5 to PW2V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 3 Control Register (PWM3) PW3E PW3V5 to PW3V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 4 Control Register (PWM4) PW4E PW4V5 to PW4V0 activate this PWM (logic 1) pulse width modulator high time Pulse Width Modulator 5 Control Register (PWM5) PW5E PW5V5 to PW5V0 activate this PWM (logic 1) pulse width modulator high time 2000 Feb 23 19 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT Pulse Width Modulator 6 Control Register (PWM6) PW6E PW6V5 to PW6V0 activate this PWM (logic 1) pulse width modulator high time FUNCTION SAA55xx Pulse Width Modulator 7 Control Register (PWM7) PW7E PW7V5 to PW7V0 ROM Bank (ROMBK) STBY Standby mode enabled (logic 1) activate this PWM (logic 1) pulse width modulator high time I2C-bus Slave Address Register (S1ADR) ADR6 to ADR0 GC I2C-bus Control Register (S1CON) CR2 to CR0 clock rate bits; CR<2:0>: 000 = 100 kHz bit rate 001 = 3.75 kHz bit rate 010 = 150 kHz bit rate 011 = 200 kHz bit rate 100 = 25 kHz bit rate 101 = 1.875 kHz bit rate 110 = 37.5 kHz bit rate 111 = 50 kHz bit rate ENSI STA enable I2C-bus interface (logic 1) START flag. When this bit is set in slave mode, the hardware checks the I2C-bus and generates a START condition if the bus is free or after the bus becomes free. If the device operates in master mode it will generate a repeated START condition. STOP flag. If this bit is set in a master mode a STOP condition is generated. A STOP condition detected on the I2C-bus clears this bit. This bit may also be set in slave mode in order to recover from an error condition. In this case no STOP condition is generated to the I2C-bus, but the hardware releases the SDA and SCL lines and switches to the not selected receiver mode. The STOP flag is cleared by the hardware. I2C-bus slave address to which the device will respond enable I2C-bus general call address (logic 1) STO 2000 Feb 23 20 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT SI FUNCTION SAA55xx Serial Interrupt flag. This flag is set and an interrupt request is generated, after any of the following events occur: * A START condition is generated in master mode * The own slave address has been received during AA = 1 * The general call address has been received while S1ADR.GC and AA = 1 * A data byte has been received or transmitted in master mode (even if arbitration is lost) * A data byte has been received or transmitted as selected slave * A STOP or START condition is received as selected slave receiver or transmitter. While the SI flag is set, SCL remains LOW and the serial transfer is suspended. SI must be reset by software. AA Assert Acknowledge flag. When this bit is set, an acknowledge is returned after any one of the following conditions: * Own slave address is received * General call address is received (S1ADR.GC = 1) * A data byte is received, while the device is programmed to be a master receiver * A data byte is received, while the device is selected slave receiver. When the bit is reset, no acknowledge is returned. Consequently, no interrupt is requested when the own address or general call address is received. I2C-bus Data Register (S1DAT) DAT7 to DAT0 I2C-bus Status Register (S1STA) STAT4 to STAT0 Software ADC Register (SAD) VHI CH1 to CH0 analog input voltage greater than DAC voltage (logic 1) ADC input channel select; CH<1:0>: 00 = ADC3 01 = ADC0 10 = ADC1 11 = ADC2 ST(1) SAD7 to SAD4 initiate voltage comparison between ADC input channel and SAD value 4 MSBs of DAC input word I2C-bus interface status I2C-bus data Software ADC Control Register (SADB) DC_COMP SAD3 to SAD0 Stack Pointer (SP) SP7 to SP0 stack pointer value enable DC comparator mode (logic 1) 4 LSBs of SAD value 2000 Feb 23 21 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT Timer/Counter Control Register (TCON) TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 FUNCTION SAA55xx Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off. Interrupt 1 edge flag (both edges generate flag). Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify edge/LOW level triggered external interrupts. Interrupt 0 edge l flag. Set by hardware when external interrupt edge detected. Cleared by hardware when interrupt processed. Interrupt 0 type flag. Set/cleared by software to specify falling edge/LOW level triggered external interrupts. 14-bit PWM MSB Register (TDACH) TPWE TD13 to TD8 14-bit PWM LSB Register (TDACL) TD7 to TD0 Timer 0 High byte (TH0) TH07 to TH00 Timer 1 High byte (TH1) TH17 to TH10 Timer 0 Low byte (TL0) TL07 to TL00 Timer 1 Low byte (TL1) TL17 to TL10 Timer 1 low byte Timer 0 low byte Timer 1 high byte Timer 0 high byte 8 LSBs of 14-bit number to be output by the 14-bit PWM activate this 14-bit PWM (logic 1) 6 MSBs of 14-bit number to be output by the 14-bit PWM Timer/Counter Mode Control (TMOD) GATE C/T M1 to M0 gating control Timer/Counter 1 Counter/Timer 1 selector mode control bits timer/counter 1; M<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in TH1 11 = stopped GATE C/T gating control Timer/Counter 0 Counter/Timer 0 selector 2000 Feb 23 22 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT M1 to M0 FUNCTION mode control bits timer/counter 0; M<1:0>: 00 = 8-bit timer or 8-bit counter with divide-by-32 prescaler 01 = 16-bit time interval or event counter SAA55xx 10 = 8-bit time interval or event counter with automatic reload upon overflow; reload value stored in TH0 11 = one 8-bit time interval or event counter and one 8-bit time interval counter Text Register 0 (TXT0) AUTO FRAME DISABLE FRAME Text Register 1 (TXT1) FIELD POLARITY H POLARITY V POLARITY Text Register 4 (TXT4) OSD BANK ENABLE QUAD WIDTH ENABLE EAST/WEST DISABLE DOUBLE HEIGHT B MESH ENABLE C MESH ENABLE TRANS ENABLE SHADOW ENABLE Text Register 5 (TXT5) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT PICTURE ON IN Text Register 6 (TXT6) BKGND OUT BKGND IN COR OUT COR IN TEXT OUT TEXT IN PICTURE ON OUT 2000 Feb 23 background colour displayed outside teletext boxes (logic 1) background colour displayed inside teletext boxes (logic 1) COR active outside teletext and OSD boxes (logic 1) COR active inside teletext and OSD boxes (logic 1) text displayed outside teletext boxes (logic 1) text displayed inside teletext boxes (logic 1) video displayed outside teletext boxes (logic 1) 23 background colour displayed outside teletext boxes (logic 1) background colour displayed inside teletext boxes (logic 1) COR active outside teletext and OSD boxes (logic 1) COR active inside teletext and OSD boxes (logic 1) text displayed outside teletext boxes (logic 1) text displayed inside teletext boxes (logic 1) video displayed outside teletext boxes (logic 1) video displayed inside teletext boxes (logic 1) alternate OSD location available via graphic attribute, additional 32 location (logic 1) enable display of quadruple width characters (logic 1) eastern character selection of character codes A0H to FFH (logic 1) disable normal decoding of double height characters (logic 1) enable meshing of black background (logic 1) enable meshing of coloured background (logic 1) display black background as video (logic 1) display shadow/fringe (default SE black) (logic 1) VSYNC pulse in second half of line during even field (logic 1) HSYNC reference edge is negative going (logic 1) VSYNC reference edge is negative going (logic 1) frame output is switched off automatically if any video displayed (logic 1) force frame output to be LOW (logic 1) Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT PICTURE ON IN Text Register 7 (TXT7) CURSOR ON DOUBLE HEIGHT BOX ON 24 BOX ON 1 - 23 BOX ON 0 Text Register 8 (TXT8) FLICKER STOP ON DISABLE SPANISH PKT 26 RECEIVED(2) WSS RECEIVED(2) WSS ON CVBS1/CVBS0 Text Register 9 (TXT9) CURSOR FREEZE CLEAR MEMORY(1) R4 to R0(2) Text Register 10 (TXT10) C5 to C0(3) Text Register 11 (TXT11) D7 to D0 Text Register 12 (TXT12) 525/625 SYNC(4) ROM VER4 to ROM VER0 VIDEO SIGNAL QUALITY Text Register 13 (TXT13) PAGE CLEARING 525 DISPLAY Text Register 17 (TXT17) FORCE ACQ1 to FORCE ACQ0 FORCE ACQ<1:0>: 00 = automatic selection 01 = force 525 timing, force 525 teletext standard 10 = force 625 timing, force 625 teletext standard 11 = force 625 timing, force 525 teletext standard software or power-on page clear in progress (logic 1) 525-line synchronisation for display (logic 1) 525-line CVBS signal is being received (logic 1) mask programmable identification for character set acquisition can be synchronised to CVBS (logic 1) current memory column value lock cursor at current position (logic 1) clear memory block pointed to by TXT15 current memory row value disable `Flicker Stopper' circuitry (logic 1) display cursor at position given by TXT9 and TXT10 (logic 1) display each character as twice normal height (logic 1) enable display of teletext boxes in memory row 24 (logic 1) enable display of teletext boxes in memory row 1 to 23 (logic 1) enable display of teletext boxes in memory row 0 (logic 1) FUNCTION video displayed inside teletext boxes (logic 1) SAA55xx disable special treatment of Spanish packet 26 characters (logic 1) packet 26 data has been processed (logic 1) wide screen signalling data has been processed (logic 1) enable acquisition of WSS data (logic 1) select CVBS1 as source for device (logic 1) data value written or read from memory location defined by TXT9, TXT10 and TXT15 2000 Feb 23 24 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT FORCE DISP1 to FORCE DISP0 FORCE DISP<1:0>: 00 = automatic selection 01 = force display to 525 mode (9 lines per row) 10 = force display to 625 mode (10 lines per row) 11 = not valid (default to 625 mode) FUNCTION SAA55xx SCREEN COL2 to SCREEN COL0 Defines colour to be displayed instead of TV picture and black background; these bits are equivalent to the RGB components. SCREEN COL<2:0>: 000 = transparent 001 = CLUT entry 9 010 = CLUT entry 10 011 = CLUT entry 11 100 = CLUT entry 12 101 = CLUT entry 13 110 = CLUT entry 14 111 = CLUT entry 15 Text Register 18 (TXT18) NOT3 to NOT0 BS1 to BS0 Text Register 19 (TXT19) TEN TC2 to TC0 TS1 to TS0 Text Register 20 (TXT20) DRCS ENABLE OSD PLANES OSD LANG ENABLE OSD LAN2 to OSD LAN0 Text Register 21 (TXT21) DISP LINES1 to DISP LINES0 the number of display lines per character row; DISP LINES<1:0>: 00 = 10 lines per character (defaults to 9 lines in 525 mode) 01 = 13 lines per character 10 = 16 lines per character 11 = reserved (logic 1) CHAR SIZE1 to CHAR SIZE0 character matrix size; CHAR SIZE<1:0>: 00 = 10 lines per character (matrix 12 x 10) 01 = 13 lines per character (matrix 12 x 13) 10 = 16 lines per character (matrix 12 x 16) 11 = reserved I2C PORT 1 enable I2C-bus Port 1 selection (P1.5/SDA1 and P1.4/SCL1) (logic 1) re-map column 9 to DRCS in TXT mode (logic 1) character code columns 8 and 9 defined as double plane characters (logic 1) enable use of OSD LAN<2:0> to define language option for display, instead of C12, C13 and C14 alternative C12, C13 and C14 bits for use with OSD menus enable twist character set (logic 1) language control bits (C12, C13 and C14) that has twisted character set twist character set selection national option table selection, maximum of 31 when used with EAST/WEST bit basic character set selection 2000 Feb 23 25 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) BIT CC ON I2C PORT 0 CC/TXT Text Register 22 (TXT22) GPF7 to GPF5 GPF4 GPF3 GPF2 GPF1 and GPF0 Watchdog Timer (WDT) WDV7 to WDV0 Watchdog Timer Key (WDTKEY) WKEY7 to WKEY0(5) XRAMP XRAMP7 to XRAMP0 Notes 1. This flag is set by software and reset by hardware. 2. Valid range TXT mode 0 to 24. 3. Valid range TXT mode 0 to 39. 4. Only valid when VIDEO SIGNAL QUALITY is set. 5. Must be set to 55H to disable Watchdog Timer when active. internal RAM access upper byte address Watchdog Timer Key value Watchdog Timer period FUNCTION closed caption acquisition on (logic 1) SAA55xx enable I2C-bus Port 0 selection (P1.7/SDA0 and P1.6/SCL0) (logic 1) display configured for CC mode (logic 1) general purpose register, bits defined by mask programmable bits reserved PWM0, PWM1, PWM2 and PWM3 output on Port 2.1 to Port 2.4 respectively (logic 1) enable closed caption acquisition (logic 1) reserved 2000 Feb 23 26 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 8.5 Character set feature bits SAA55xx Features available on the OSD only devices are reflected in a specific area of the Character ROM. These sections of the Character ROM are mapped to two Special Function Registers: TXT22 and TXT12. Character ROM address 09FEH is mapped to SFR TXT22 as shown in Table 4. Character ROM address 09FFH is mapped to SFR TXT12 as shown in Table 6. Table 4 Character ROM - TXT22 mapping U = used; X = reserved MAPPED ITEMS Character ROM address 09FEH Mapped to TXT22 Table 5 11 X - 10 X - 9 X - 8 X - 7 X 7 6 X 6 5 X 5 4 X 4 3 U 3 2 U 2 1 X 1 0 X 0 Description of Character ROM address 09FEH bits BIT 0 to 1 2 3 DESCRIPTION reserved; normally all set to logic 1 1 = enable CC acquisition 0 = disable CC acquisition 1 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 2.1 to Port 2.4 respectively 0 = PWM0, PWM1, PWM2 and PWM3 output routed to Port 3.0 to Port 3.3 respectively reserved; normally all set to logic 1 4 to 11 Table 6 Character ROM - TXT12 mapping U = used; X = reserved MAPPED ITEMS Character ROM address 09FFH Mapped to TXT12 Table 7 11 X - 10 X - 9 X - 8 X - 7 X - 6 X - 5 X - 4 X 6 3 X 5 2 X 4 1 X 3 0 X 2 Description of Character ROM address 09FFH bits BIT DESCRIPTION reserved; normally all set to logic 1 0 to 11 2000 Feb 23 27 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 8.6 External (auxiliary) memory 8.6.1 AUXILIARY RAM PAGE SELECTION SAA55xx The normal 80C51 external memory area has been mapped internally to the device, this means that the MOVX instruction accesses memory internal to the device. The Auxiliary RAM page pointer is used to select one of the 256 pages within the Auxiliary RAM, not all pages are allocated; refer to Fig.9 for further detail. A page consists of 256 consecutive bytes. handbook, halfpage 7FFFH FFFFH 8C00H 8BFFH DYNAMICALLY REDEFINABLE CHARACTERS 8800H 87FFH DISPLAY REGISTERS 87F0H 871FH CLUT 2400H 23FFH DISPLAY RAM FOR TEXT OSD (1) 2000H 84FFH ADDITIONAL DATA RAM 8460H 845FH DISPLAY RAM FOR CLOSED CAPTION (1) 8000H GSA009 8700H 02FFH DATA RAM 0000H lower 32 kbytes upper 32 kbytes (1) Display RAM for Closed Caption and Text is shared. Fig.9 Auxiliary RAM allocation. 2000 Feb 23 28 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth FFH 00H FFH 00H MOVX @ Ri,A MOVX A, @ Ri FFH 00H FFH 00H SFR XRAMP = 00H MBK958 FFFFH SFR XRAMP = FFH FF00H FEFFH SFR XRAMP = FEH FE00H MOVX @ DPTR,A MOVX A, @ DPTR 01FFH SFR XRAMP = 01H 0100H 00FFH 0000H Fig.10 Indirect addressing of Auxiliary RAM. 2000 Feb 23 29 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 9 REDUCED POWER MODES SAA55xx There are three power saving modes: Standby, Idle and Power-down, incorporated into the OSD only device. When utilizing any of these modes, power to the device (VDDP, VDDC and VDDA) should be maintained, since power saving is achieved by clock gating on a section by section basis. 9.1 Idle mode * The third method of terminating Idle mode is with an external hardware reset. Since the oscillator is running, the hardware reset need only be active for two machine cycles (24 clocks at 12 MHz) to complete the reset operation. Reset defines all SFRs and Display memory to an initialized state, but maintains all other RAM values. Code execution commences with the Program Counter set to `0000'. 9.2 Power-down mode During Idle mode, Acquisition, Display and the Central Processing Unit (CPU) sections of the device are disabled. The following functions remain active: * Memory interface * I2C-bus interface * Timer/Counters * Watchdog Timer * Pulse Width Modulators. To enter Idle mode the IDL bit in the PCON register must be set. The Watchdog Timer must be disabled prior to entering the Idle mode to prevent the device being reset. Once in Idle mode, the crystal oscillator continues to run, but the internal clock to the CPU, Acquisition and Display are gated out. However, the clocks to the Memory interface, I2C-bus interface, timer/counters, Watchdog Timer and Pulse Width Modulators are maintained. The CPU state is frozen along with the status of all SFRs, internal RAM contents are maintained, as are the device output pin values. Since the output values on Red Green Blue (RGB) and the Video Data Switch (VDS) are maintained the display output must be disabled before entering this mode. There are three methods to recover from Idle mode: * Assertion of an enabled interrupt will cause the IDL bit to be cleared by hardware, thus terminating Idle mode. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Idle mode. * A second method of exiting the Idle mode is via an interrupt generated by the Software Analog-to-Digital (SAD) DC Compare circuit. When the device is configured in this mode, detection of an analog threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle mode. In Power-down mode the crystal oscillator is stopped. The contents of all SFRs and Data memory are maintained, However, the contents of the Auxiliary/Display memory are lost. The port pins maintain the values defined by their associated SFRs. Since the output values on RGB and VDS are maintained the display output must be made inactive before entering Power-down mode. The Power-down mode is activated by setting the PD bit in the PCON register. It is advised to disable the Watchdog Timer prior to entering Power-down. There are three methods of exiting Power-down mode: * An external interrupt provides the first mechanism for waking from Power-down. Since the clock is stopped, external interrupts need to be set level sensitive prior to entering Power-down. The interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one after the instruction that put the device into Power-down mode. * A second method of exiting power-down is via an interrupt generated by the SAD DC Compare circuit. When the device is configured in this mode, detection of a certain analog threshold at the input to the SAD may be used to trigger wake-up of the device i.e. TV Front Panel Key-press. As above, the interrupt is serviced, and following the instruction RETI, the next instruction to be executed will be the one following the instruction that put the device into the Power-down. * The third method of terminating the Power-down mode is with an external hardware reset. Reset defines all SFRs and Display memory, but maintains all other RAM values. Code execution commences with the Program Counter set to `0000'. 2000 Feb 23 30 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 9.3 Standby mode 10.2.1 OPEN-DRAIN SAA55xx When Standby mode is entered both Acquisition and Display sections are disabled. The following functions remain active: * 80C51 core * Memory interface * I2C-bus interface * Timer/Counters * Watchdog Timer * Software ADC * Pulse Width Modulators To enter Standby mode, the STANDBY control bit in the ROMBK SFR (bit 7) must be set. It can be used in conjunction with either Idle or Power-down modes to switch between power saving modes. This mode enables the 80C51 core to decode either IR remote commands or receive I2C-bus commands without the device being fully powered. The Standby state is maintained upon exit from either the Idle mode or Power-down mode. No wake-up from Standby is necessary as the 80C51 core remains operational. Since the output values on RGB and VDS are maintained the display output must be disabled before entering this mode. 10 I/O FACILITY 10.1 I/O ports The open-drain configuration can be used for bidirectional operation of a port. It requires an external pull-up resistor, the pull-up voltage has a maximum value of 5.5 V, to allow connection of the device into a 5 V environment. Note that the I2C-bus ports (P1.4, P1.5, P1.6 and P1.7) can only be configured as open-drain. 10.2.2 QUASI-BIDIRECTIONAL The quasi-bidirectional configuration is a combination of open-drain and push-pull. It requires an external pull-up resistor to VDDP (nominally 3.3 V). When a signal transition from LOW-to-HIGH is output from the device, the pad is put into push-pull configuration for one clock cycle (166 ns) after which the pad goes into open-drain configuration. This configuration is used to speed up the edges of signal transitions. This is the default state of operation of the pads after reset. 10.2.3 HIGH-IMPEDANCE The high-impedance configuration can be used for input only operation of the port. When using this configuration the two output transistors are turned off. 10.2.4 PUSH-PULL The push-pull configuration can be used for output only. In this configuration the signal is driven to either 0 V or VDDP, which is nominally 3.3 V. 10.3 Port alternative functions The SAA55xx devices have 29 I/O lines, each is individually addressable, or form 3 parallel 8-bit addressable ports which are Port 0, Port 1 and Port 2. Port 3 has 5-bit parallel I/Os only. 10.2 Port type Ports 1, 2 and 3 are shared with alternative functions to enable control of external devices and circuitry. The alternative functions are enabled by setting the appropriate SFR and also writing a logic 1 to the port bit that the function occupies. 10.4 LED support All individual ports can be programmed to function in one of four I/O configurations: open-drain, quasi-bidirectional, high-impedance and push-pull. The I/O configuration is selected using two associated Port Configuration Registers: PnCFGA and PnCFGB (where n = port number 0, 1, 2 or 3); see Table 3. Port pins P0.5 and P0.6 have a 8 mA current sinking capability to enable LEDs in series with current limiting resistors to be driven directly, without the need for additional buffering circuitry. 2000 Feb 23 31 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 11 INTERRUPT SYSTEM The device has six interrupt sources, each of which can be enabled or disabled. When enabled each interrupt can be assigned one of two priority levels. There are four interrupts that are common to the 80C51, two of these are external interrupts (EX0 and EX1) and the other two are timer interrupts (ET0 and ET1). In addition to the conventional 80C51, one application specific interrupt is incorporated internal to the device which has following functionality: * Display Busy interrupt (EBUSY). An interrupt is generated when the display enters either a Horizontal or Vertical Blanking Period. i.e. indicates when the microcontroller can update the display RAM without causing undesired effects on the screen. This interrupt can be configured in one of two modes using the MMR Configuration (address 87FFH, bit TXT/V): - Text Display Busy. An interrupt is generated on each active horizontal display line when the Horizontal Blanking Period is entered - Vertical Display Busy. An interrupt is generated on each vertical display field when the Vertical Blanking period is entered. 11.1 Interrupt enable structure 11.3 SAA55xx If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus, within each priority level there is a second priority structure determined by the polling sequence as defined in Table 8. Table 8 Interrupt priority (within same level) PRIORITY WITHIN LEVEL highest - - - - lowest INTERRUPT VECTOR 0003H 000BH 0013H 001BH 002BH 0033H SOURCE EX0 ET0 EX1 ET1 ES2 EBUSY Interrupt vector address The processor acknowledges an interrupt request by executing a hardware generated LCALL to the appropriate servicing routine. The interrupt vector addresses for each source are shown in Table 8. 11.4 Level/edge interrupt Each of the individual interrupts can be enabled or disabled by setting or clearing the relevant bit in the Interrupt Enable Register (IE). All interrupt sources can also be globally disabled by clearing the EA bit (IE.7). 11.2 Interrupt enable priority The external interrupt can be programmed to be either level-activated or transition-activated by setting or clearing the IT0/IT1 bits in the Timer Control SFR (TCON). Table 9 ITx 0 1 - External interrupt activation LEVEL active LOW - INT0 = negative edge INT1 = positive and negative edge EDGE Each interrupt source can be assigned one of two priority levels. The interrupt priorities are defined by the Interrupt Priority Register (IP). A low priority interrupt can be interrupted by a high priority interrupt, but not by another low priority interrupt. A high priority interrupt can not be interrupted by any other interrupt source. If two requests of different priority level are received simultaneously, the request with the highest priority level is serviced. The external interrupt INT1 differs from the standard 80C51 interrupt in that it is activated on both edges when in edge sensitive mode. This is to allow software pulse width measurement for handling remote control inputs. 2000 Feb 23 32 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth EX0 H1 L1 H2 L2 H3 L3 H4 L4 H5 L5 H6 L6 source enable SFR IE<0:6> global enable SFR IE.7 priority control SFR IP<0:6> highest priority level 1 highest priority level 0 ET0 EX1 ET1 ES2 EBUSY lowest priority level 1 lowest priority level 0 GSA033 interrupt source Fig.11 Interrupt structure. 2000 Feb 23 33 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 12 TIMER/COUNTER Two 16-bit timers/counters are incorporated Timer 0 and Timer 1. Both can be configured to operate as either timers or event counters. In Timer mode, the register is incremented on every machine cycle. It is therefore counting machine cycles. Since the machine cycle consists of twelve oscillator periods, the count rate is 112fosc = 1 MHz. In Counter mode, the register is incremented in response to a negative transition at its corresponding external pin T0 or T1. Since the pins T0 and T1 are sampled once per machine cycle, it takes two machine cycles to recognise a transition, this gives a maximum count rate of 1 f 24 osc = 0.5 MHz. There are six Special Function Registers used to control the timers/counters. These are: TCON, TMOD, TL0, TH0, TL1 and TH1. The timer/counter function is selected by control bits C/T in the Timer Mode SFR (TMOD). These two Timer/Counters have four operating modes, which are selected by bit-pairs (M1 and M0) in TMOD. Detail of the modes of operation is given in "Handbook IC20, 80C51-Based 8-bit Microcontrollers". TL0 and TH0 are the actual Timer/Counter registers for Timer 0. TL0 is the low byte and TH0 is the high byte. TL1 and TH1 are the actual Timer/Counter registers for Timer 1. TL1 is the low byte and TH1 is the high byte. 13 WATCHDOG TIMER The Watchdog Timer is a counter that once in an overflow state forces the microcontroller into a reset condition. The purpose of the Watchdog Timer is to reset the microcontroller if it enters an erroneous processor state (possibly caused by electrical noise or RFI) within a reasonable period of time. When enabled, the Watchdog circuitry will generate a system reset if the user program fails to reload the Watchdog Timer within a specified length of time known as the Watchdog Interval (WI). The Watchdog Timer consists of an 8-bit counter with an 11-bit prescaler. The prescaler is fed with a signal whose frequency is 112fosc (1 MHz for 12 MHz oscillator). SAA55xx The 8-bit timer is incremented every `t' seconds where: 1 1 t = 12 x 2048 x -------- = 12 x 2048 x --------------------- = 2.048 ms 6 f osc 12 x 10 13.1 Watchdog Timer operation The Watchdog operation is activated when the WLE bit in the Power Control SFR (PCON) is set. The Watchdog can be disabled by software by loading the value 55H into the Watchdog Timer Key SFR (WDTKEY). This must be performed before entering the Idle or Power-down mode to prevent exiting the mode prematurely. Once activated the Watchdog Timer SFR (WDT) must be reloaded before the timer overflows. The WLE bit must be set to enable loading of the WDT SFR, once loaded the WLE bit is reset by hardware, this is to prevent erroneous software from loading the WDT SFR. The value loaded into the WDT defines the Watchdog Interval (WI). WI = ( 256 - WDT ) x t = ( 256 - WDT ) x 2.048 ms The range of intervals is from WDT = 00H which gives 524 ms to WDT = FFH which gives 2.048 ms. 14 PULSE WIDTH MODULATORS The device has eight 6-bit Pulse Width Modulated (PWM) outputs for analog control of e.g. volume, balance, bass, treble, brightness, contrast, hue and saturation. The PWM outputs generate pulse patterns with a repetition rate of 21.33 s, with the high time equal to the PWM SFR value multiplied by 0.33 s. The analog value is determined by the ratio of the high time to the repetition time, a D.C. voltage proportional to the PWM setting is obtained by means of an external integration network (low-pass filter). 14.1 PWM control The relevant PWM is enabled by setting the PWM enable bit PWxE in the PWMx Control Register (where x = 0 to 7). The high time is defined by the value PWxV<5:0>. 2000 Feb 23 34 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 14.2 Tuning Pulse Width Modulator (TPWM) 3.3 256 SAA55xx The device has a single 14-bit PWM that can be used for Voltage Synthesis Tuning. The method of operation is similar to the normal PWM except that the repetition period is 42.66 s. 14.3 TPWM control Two SFRs are used to control the TPWM, they are TDACL and TDACH. The TPWM is enabled by setting the TPWE bit in the TDACH SFR. The most significant bits TD<13:7> alter the high period between 0 and 42.33 s. The seven least significant bits TD<6:0> extend certain pulses by a further 0.33 s, e.g. if TD<6:0> = 01H then 1 in 128 periods will be extended by 0.33 s, if TD<6:0> = 02H then 2 in 128 periods will be extended. The TPWM will not start to output a new value until TDACH has been written to. Therefore, if the value is to be changed, TDACL should be written before TDACH. 14.4 Software ADC (SAD) The resolution of the DAC voltage with a nominal value is 13 mV. The external analog voltage has a lower value equivalent to VSSA and an upper value equivalent to VDDP - Vtn, where Vtn is the threshold voltage for an N type Metal Oxide Semiconductor transistor. The reason for this is that the input pins for the analog signals (P3.0 to P3.3) are 5 V tolerant for normal port operations, i.e. when not used as analog input. To protect the analog multiplexer and comparator circuitry from the 5 V, a series transistor is used to limit the voltage. This limiting introduces a voltage drop equivalent to Vtn (0.6 V) on the input voltage. The maximum value of Vtn is 0.75 V, therefore for worst case calculations, the maximum input to the SAD should be calculated as VDD(min) - 0.75 V. Therefore, for an input voltage in the range VDDP to VDDP - Vtn the SAD returns the same comparison value. 14.4.3 SAD DC COMPARATOR MODE Four successive approximation Analog-to-Digital Converters can be implemented in software by making use of the on-board 8-bit Digital-to-Analog Converter and Analog Comparator. 14.4.1 SAD CONTROL The SAD module incorporates a DC Comparator mode which is selected using the DC_COMP control bit in the SADB SFR. This mode enables the microcontroller to detect a threshold crossing at the input to the selected analog input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) of the software ADC. A level sensitive interrupt is generated when the analog input voltage level at the pin falls below the analog output level of the SAD DAC. This mode is intended to provide the device with a wake-up mechanism from Power-down or Idle mode when a key-press on the front panel of the TV is detected. The following software sequence should be used when utilizing this mode for Power-down or Idle: 1. Disable INT1 using the IE SFR. 2. Set INT1 to level sensitive using the TCON SFR. 3. Set the DAC digital input level to the desired threshold level using SAD/SADB SFRs and select the required input pin (P3.0/ADC0, P3.1/ADC1, P3.2/ADC2 or P3.3/ADC3) using CH<1:0> in the SAD SFR. 4. Enter DC Compare mode by setting the DC_COMP enable bit in the SADB SFR. 5. Enable INT1 using the IE SFR. 6. Enter Power-down/Idle mode. Upon wake-up the SAD should be restored to its conventional operating mode by disabling the DC_COMP control bit. The control of the required analog input is done using the channel select bits CH<1:0> in the SAD SFR, this selects the required analog input to be passed to one of the inputs of the comparator. The second comparator input is generated by the DAC whose value is set by the bits SAD<7:0> in the SAD and SADB SFRs. A comparison between the two inputs is made when the start compare bit ST in the SAD SFR is set, this must be at least one instruction cycle after the SAD<7:0> value has been set. The result of the comparison is given on VHI one instruction cycle after the setting of ST. 14.4.2 SAD INPUT VOLTAGE The external analog voltage that is used for comparison with the internally generated DAC voltage does not have the same voltage range. The DAC has a lower reference level of VSSA and an upper reference level of VDDP. 2000 Feb 23 35 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, halfpage VDDP ADC0 ADC1 ADC2 ADC3 CH<1:0> VHI MUX 4:1 SAD<3:0> 8-BIT DAC SADB<3:0> MBK960 Fig.12 SAD block diagram. 2000 Feb 23 36 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 15 I2C-BUS SERIAL I/O The I2C-bus consists of a serial data (SDA) line and a serial clock (SCL) line. The definition of the I2C-bus protocol can be found in the document "The I2C-bus and how to use it (including specification)". This document may be ordered using the code 9398 393 40011. The device operates in four modes: * Master transmitter * Master receiver * Slave transmitter * Slave receiver. The microcontroller peripheral is controlled by the Serial Control SFR (S1CON) and its status is indicated by the Status SFR (S1STA). Information is transmitted/received to/from the I2C-bus using the Data SFR (S1DAT) and the Slave Address SFR (S1ADR) is used to configure the slave address of the peripheral. The byte level I2C-bus serial port is identical to the I2C-bus serial port on the P8xCE558, except for the clock rate selection bits CR<2:0> in S1CON. The operation of the subsystem is described in detail in the "P8xCE558 data sheet". 15.1 I2C-bus port selection 16.1 Memory structure SAA55xx The memory is partitioned into two distinct areas, the dedicated Auxiliary RAM area, and the Display RAM area. The Display RAM area when not being used for Data Capture or Display can be used as an extension to the auxiliary RAM area. 16.1.1 AUXILIARY RAM The Auxiliary RAM is not initialised at power-up. Application software must initialize this Auxiliary RAM. The contents of the Auxiliary RAM area, and the Display RAM are maintained during Standby and Idle modes, but are lost if Power-down mode is entered. 16.1.2 DISPLAY RAM The Display RAM (Block 0 only) is initialised on power-up to a value of 20H. The contents of the Display RAM are maintained when entering Idle mode. If Idle mode is exited using an interrupt then the contents are unchanged, if Idle mode is exited using a reset then the contents are re-initialised to 20H. Full Closed Caption display requires a display RAM from 8000H to 845FH. The memory from 8460H to 84FFH (must be initialized by the application software) can be utilized as an extension to the dedicated contiguous Auxiliary RAM that occupies 000H to 02FFH. 16.2 Memory mapping Two I2C-bus ports are available SCL0/SDA0 and SCL1/SDA1. The selection of the port is done using TXT21.I2C PORT 0 and TXT21.I2C PORT 1. When the port is enabled, any information transmitted from the device goes onto the enabled port. Any information transmitted to the device can only be acted on if the port is enabled. If both ports are enabled then data transmitted from the device is seen on both ports, however data transmitted to the device on one port can not be seen on the other port. 16 MEMORY INTERFACE The memory interface controls access to the embedded DRAM, refreshing of the DRAM and page clearing. The DRAM is shared between Data Capture, display and microcontroller sections. The Data Capture section uses the DRAM to store acquired information that has been requested. The display reads from the DRAM information and converts it into RGB values. The microcontroller uses the DRAM as embedded auxiliary RAM. The dedicated Auxiliary RAM area occupies 0.75 kbytes, with an address range from 0000H to 02FFH. The Display RAM occupies 1.25 kbytes with an address range from 2000H to 24FFH for TXT mode and 8000H to 84FFH for CC mode. The two modes although having different address ranges occupy the same physical DRAM area. The hardware will only initialize 1-kbyte (block 0) of the available 1.25 kbytes on the device. The application software must initialize this additional 0.25 kbytes if it is to be used as display RAM or auxiliary RAM. 2000 Feb 23 37 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 16.3 Addressing memory 16.4 Page clearing SAA55xx The memory can be addressed by the microcontroller in two ways, either directly using a MOVX command, or via Special Function Registers depending on what address is required. The dedicated Auxiliary RAM, and Display memory in the range 8000H to 84FFH, can only be accessed using the MOVX command. The Display memory in the range 2000H to 23FFH can either be directly accessed using the MOVX, or via the Special Function Registers. 16.3.1 TXT DISPLAY MEMORY SFR ACCESS Page clearing is performed on request from the microcontroller under the control of the embedded software. At power-on and reset the Text Display memory (from 2000H to 23FFH) is cleared to the value of 20H. The TXT13.PAGE CLEARING bit will be set while this takes place. 16.4.1 DATA CAPTURE PAGE CLEAR Not present in the SAA55xx OSD only devices. 16.4.2 SOFTWARE PAGE CLEAR The Display memory when in TXT mode (see Fig.14) is configured as 40 columns wide by 25 rows and occupies 1K x 8 bits of memory. The row and column is selected using TXT9.R<4:0> and TXT10.C<5:0>. The data at the selected position can be read or written using TXT11.D<7:0>. Whenever a read or write is performed on TXT11, the row values stored in TXT9 and column value stored in TXT10 are automatically incremented. For rows 0 to 24 the column value is incremented up to a maximum of 39, at which point it resets to a logic 0 and increments the row counter value. When row 25 column 23 is reached the values of the row and column are both reset to logic 0. Writing values outside of the valid range for TXT9 or TXT10 will cause undetermined operation of the auto-incrementing function for accesses to TXT11. 16.3.2 TXT DISPLAY MEMORY MOVX ACCESS The software can also initiate a page clear, by setting the TXT9.CLEAR MEMORY bit. The CLEAR MEMORY bit is not latched so the software does not have to reset it after it has been set. Only one page can be cleared in a TV line so if the software requests a page clear it will be carried out on the next TV line on which the Data Capture hardware does not force the page to be cleared. A flag, TXT13.PAGE CLEARING, is provided to indicate that a software requested page clear is being carried out. The flag is set when a logic 1 is written into the TXT9.CLEAR MEMORY bit and is reset when the page clear has been completed. Inventory page clearing in not present in the SAA55xx OSD only devices. It is important for the generation of OSD displays, that use this mode of access, to understand the mapping of the MOVX address onto the display row and column value. This mapping of row and column onto address is shown in Table 10. The values shown are added onto a base address for the required memory block (see Fig.13) to give a 16-bit address. Table 10 Column and row to MOVX address (lower 10 bits of address) ROW Row 0 Row 1 ... Row 23 Row 24 Row 25 COL.0 000H 020H ... 2E0H 300H 320H ... ... ... ... ... ... ... COL.23 017H 037H ... 3F7H 317H 337H ... ... ... ... ... ... ... COL.31 01FH 03FH ... 2FFH 31FH COL.32 3F8H 3F0H ... 340H 338H ... ... ... ... ... ... ... COL.39 3FFH 3F7H ... 347H 33FH 2000 Feb 23 38 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx lower 32 kbytes handbook, halfpage upper 32 kbytes 7FFFH FFFFH 23FFH TEXT DISPLAY 2000H 84FFH 02FFH AUXILIARY 0000H CC DISPLAY GSA011 8000H Fig.13 DRAM memory mapping. 2000 Feb 23 39 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 control data 10 C Column 20 30 39 9 10 23 non-displayable data (byte 10 reserved) active position TXT9.R<4:0> = 01H, TXT10.C<5:0> = 0AH, TXT11 = 43H MBK962 Fig.14 TXT memory map. 2000 Feb 23 40 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 17 DATA CAPTURE The Data Capture section takes in the analog Composite Video and Blanking Signal (CVBS), and from this extracts the required data, which is then decoded and stored in memory. The extraction of the data is performed in the digital domain. The first stage is to convert the analog CVBS signal into a digital form. This is done using an ADC sampling at 12 MHz. The data and clock recovery is then performed by a Multi-Rate Video Input Processor (MulVIP). From the recovered data and clock, the serial Closed Captioning data is converted to parallel and stored as two bytes per line. The extracted data is stored in SFR locations. 17.1 Data Capture features 17.1.4 DATA CAPTURE TIMING SAA55xx The Data Capture timing section uses the synchronisation information extracted from the CVBS signal to generate the required horizontal and vertical reference timings. The timing section automatically recognizes and selects the appropriate timings for either 625 (50 Hz) synchronisation or 525 (60 Hz) synchronisation. A flag TXT12.VIDEO SIGNAL QUALITY is set when the timing section is locked correctly to the incoming CVBS signal. When TXT12.VIDEO SIGNAL QUALITY is set another flag TXT12.525/625 SYNC can be used to identify the standard. 17.1.5 LINE 21 DATA SERVICES * Two CVBS inputs * Data Capture for Line 21 Data Service * Video Signal Quality Detector. 17.1.1 CVBS SWITCH The Line 21 Data Services is transmitted on line 21 of a 525-line broadcast system and is used for Captioning information, Text information and Extended Data Services. Full Details can be found in "Recommended Practise for Line 21 Data Service EIA-608". Closed Caption Line 21 data is only acquired when TXT21.CC ON bit is set. Two bytes of data are stored per field in SFRs, the first bye is stored in CCDAT1 and the second byte is stored in CCDAT2. The contents of each CCDAT register are reset to 00H at the start of the Closed Caption line defined by CCLIN.CS<4:0>. At the end of the Closed Caption line an interrupt is generated if IE.ECC is active. The processing of the Closed Caption data to convert into a displayable format is performed by software. The CVBS switch is used to select the required analog input depending on the value of TXT8.CVBS1/CVBS0. 17.1.2 ANALOG-TO-DIGITAL CONVERTER The output of the CVBS switch is passed to a differential to single ended converter, although in this device it is used in single ended configuration with a reference. The analog output of the differential to single ended converter is converted into a digital representation by a full-flash ADC with a sampling rate of 12 MHz. 17.1.3 MULTI-RATE VIDEO INPUT PROCESSOR The multi-rate video input processor is a Digital Signal Processor designed to extract the data and recover the clock from a digitized CVBS signal. The only data and clock standard that can be recovered in the OSD only devices is Closed Caption at a data rate of approximately 503.5 kHz. 2000 Feb 23 41 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth CVBS0 CVBS1 CVBS SWITCH CVBS ADC data<7:0> DATA SLICER AND CLOCK RECOVERY TTC TTD SYNC SEPARATOR VCS ACQUISITION TIMING SYNC_FILTER ACQUISITION FOR CC/WSS output data to SFRs GSA010 Fig.15 Data Capture block diagram. 18 DISPLAY The display section is based on the requirements for US Closed Caption. There are some enhancements for use with locally generated On-Screen Displays. The display section reads the contents of the Display memory and interprets the control/character codes. From this information and other global settings, the display produces the required RGB signals and video/data (Fast Blanking) signal for a TV signal processing device. The display is synchronised to the TV signal processing device by way of horizontal and vertical sync signals provided by external circuits (Slave Sync mode). From these signals all display timings are derived. 18.1 Display features * Globally selectable scan lines per row 9, 10, 13 or 16 * Globally selectable character matrix (H x V) 12 x 9, 12 x 10, 12 x 13 or 12 x 16 * Italics * Soft colours using CLUT with 4096 colour palette * Underline * Overline * Fringing (shadow) selectable from N-S-E-W direction * Fringe colour selectable * Meshing of defined area * Contrast reduction of defined area * Cursor * Special Graphics characters with two planes, allowing four colours per character * 32 software redefinable On-Screen Display characters * 4 WST character sets (G0/G2) in single device (e.g. Latin, Cyrillic, Greek, Arabic) * G1 Mosaic graphics, Limited G3 Line drawing characters * WST character sets and Closed (including extended) Caption character set in a single device. 42 * Teletext style OSD and Enhanced OSD modes * US Closed Caption features * Serial and Parallel display attributes * Single/double/quadruple width and height for characters * Scrolling of display region * Variable flash rate controlled by software 2000 Feb 23 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth CLK VSYNC HSYNC DISPLAY TIMING address MICROPROCESSOR INTERFACE data FUNCTION REGISTERS address to memory interface from memory interface address data data DISPLAY DATA ADDRESSING ATTRIBUTE HANDLING address data control PARALLEL/SERIAL CONVERTER AND FRINGING DATA BUFFER CHARACTER ROM AND DRCs data CHARACTER FONT ADDRESSING CLUT RAM address DAC DAC DAC MBK965 R G B FB Fig.16 Display block diagram. 2000 Feb 23 43 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.2 Display modes SAA55xx The display section has two distinct modes with different features available in each. The two modes are: * TXT: This is the display configured for WST with additional serial and global attributes. The display is configured as a fixed 25 rows with 40 characters per row. In the OSD only family this mode can only be utilised for display of Text style OSD, no Teletext Data Capture is present. * CC: This is the display configured as the US Closed Caption mode. The display is configured as a maximum of 16 rows with a maximum of 48 characters per row. In both of the above modes the character matrix, and TV lines per row can be defined. There is an option of 9, 10, 13 and 16 TV lines per display row, and a character matrix (H x V) of 12 x 9, 12 x 10, 12 x 13 or 12 x 16. Not all combinations of TV lines per row and maximum display rows give a sensible OSD display, since there is a limited number of TV scan lines available. Special Function Register TXT21 and memory mapped registers are used to control the mode selection. 18.3 Display feature descriptions TXT: This attribute is set by the control character `flash' (08H) and remains valid until the end of the row or until reset by the control character `steady' (09H). 18.3.2 BOXES CC: This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then it is set from the next character onwards. In Text mode (within CC mode) the background colour is displayed regardless of the setting of the box attribute bit. Boxes take effect only during mixed mode, where boxes are set in this mode the background colour is displayed. Character locations where boxes are not set show video/screen colour (depending on the setting in the MMR Display Control) instead of the background colour. TXT: Two types of boxes exist, the teletext box and the OSD box. The teletext box is activated by the `start box' control character (0BH). Two start box characters are required to begin a teletext box, with the box starting between the 2 characters. The box ends at the end of the line or after a `end box' control character. TXT mode can also use OSD boxes, they are started using size, implying OSD control characters (BCH, BDH, BEH and BFH). The box starts after the control character (set after) and ends either at the end of the row or at the next size implying OSD character (set at). The attributes flash, teletext box, conceal, separate graphics, twist and hold graphics are all reset at the start of an OSD box, as they are at the start of the row. OSD boxes are only valid in TV mode which is defined by TXT5 = 03H and TXT6 = 03H. All display features are now described in detail for both TXT and CC modes. 18.3.1 FLASH Flashing causes the foreground colour pixel to be displayed as the background pixels.The flash frequency is controlled by software setting and resetting the MMR Status (see Table 28) at the appropriate interval. CC: This attribute is valid from the time set (see Table 16) until the end of the row or until otherwise modified. 2000 Feb 23 44 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.3.3 SIZE SAA55xx The size of the characters can be modified in both the horizontal and vertical directions. CC: Two sizes are available in both the horizontal and vertical directions. The sizes available are normal (x1), double (x2) height/width and any combination of these. The attribute setting is always valid for the whole row. Mixing of sizes within a row is not possible. TXT: Three horizontal sizes are available normal (x1), double (x2) and quadruple (x4). The control characters `normal size' (0CH/BCH) enables normal size, the `double width' or `double size' (0EH/BEH/0FH/BFH) enables double width characters. Any two consecutive combination of `double width' or `double size' (0EH/BEH/0FH/BFH) activates quadruple width characters, provided quadruple width characters are enabled by TXT4.QUAD WIDTH ENABLE. Three vertical sizes are available normal (x1), double (x2) and quadruple (x4). The control characters `normal size' (0CH/BCH) enable normal size, the `double height' or `double size' (0DH/BDH/0FH/BFH) enable double height characters. Quadruple height characters are achieved by using double height characters and setting the global attributes TXT7.DOUBLE HEIGHT (expand) and TXT7.BOTTOM/TOP. If double height characters are used in Teletext mode, single height characters in the lower row of the double height character are automatically disabled. 18.3.4 ITALIC CC: This attribute is valid from the time set until the end of the row or otherwise modified. The attribute causes the character foreground pixels to be offset horizontally by 1 pixel per 4 scan lines (interlaced mode). The base is the bottom left character matrix pixel. The pattern of the character is indented as shown in Fig.17. TXT: The Italic attribute is not available. handbook, full pagewidth 12 x 16 character matrix 12 x 13 character matrix 12 x 10 character matrix 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 0 2 4 6 8 10 indented by 7/6/4 indented by 6/5/3 indented by 5/4/2 indented by 4/3/1 indented by 3/2/0 indented by 2/1 indented by 1/0 indented by 0 MBK970 Field 1 Field 2 Fig.17 Italic characters. 2000 Feb 23 45 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.3.5 COLOURS 18.3.7 BACKGROUND COLOUR SAA55xx A CLUT (Colour Look-Up Table) with 16 colour entries is provided. The colours are programmable out of a palette of 4096 (4 bits per R, G and B). The CLUT is defined by writing data to a RAM that resides in the MOVX address space of the 80C51. Table 11 CLUT colour values RED<3:0> GREEN<3:0 BLUE<3:0> (B11 TO B8) >(B7 TO B4) (B3 TO B0) 0000 0000 .... 1111 1111 18.3.6 0000 0000 .... 1111 1111 0000 1111 .... 0000 1111 COLOUR ENTRY 0 1 .... 14 15 CC: This attribute is valid from the time set until end of row or otherwise modified if set with Serial Mode 0. If set with Serial Mode 1, then the colour is set from the next character onwards. The background colour can be chosen from all 16 CLUT entries. TXT: The control character `new background' (1DH) is used to change the background colour to the current foreground colour. The selection is immediate (set at) and remains valid until the end of the row or until otherwise modified. The Text background control characters map to the CLUT entries as shown in Table 13. Table 13 Background CLUT mapping FOREGROUND COLOUR CC: The foreground colour can be chosen from 8 colours on a character-by-character basis. Two sets of 8 colours are provided. A serial attribute switches between the banks (see Table 16, Serial Mode 1, bit 7). The colours are the CLUT entries 0 to 7 or 8 to 15. TXT: The foreground colour is selected via a control character (see Table 16). The colour control characters take effect at the start of the next character (set-after) and remain valid until the end of the row, or until modified by a control character. Only 8 foreground colours are available. The text foreground control characters map to the CLUT entries is shown in Table 12. Table 12 Foreground CLUT mapping CONTROL CODE 00H 01H 02H 03H 04H 05H 06H 07H DEFINED COLOUR black red green yellow blue magenta cyan white CLUT ENTRY 0 1 2 3 4 5 6 7 CONTROL CODE 00H + 1DH 01H + 1DH 02H + 1DH 03H + 1DH 04H + 1DH 05H + 1DH 06H + 1DH 07H + 1DH 18.3.8 DEFINED COLOUR black red green yellow blue magenta cyan white CLUT ENTRY 8 9 10 11 12 13 14 15 BACKGROUND DURATION The attribute when set takes effect from the current position until the end of the text display defined in the MMR Text Area End. CC: The background duration attribute (see Table 16, Serial Mode 1, bit 8) in combination with the End Of Row attribute (see Table 16, Serial Mode 1, bit 9) forces the background colour to be displayed on the row until the end of the text area is reached. TXT: This attribute is not available. 2000 Feb 23 46 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.3.9 UNDERLINE SAA55xx The underline attribute causes the characters to have the bottom scan line of the character cell forced to foreground colour, including spaces. If background duration is set, then underline is set until the end of the text area. CC: The underline attribute (see Table 16, Serial Mode 0/1, bit 4) is valid from the time set until the end of row or otherwise modified. TXT: This attribute is not available. 18.3.10 OVERLINE The overline attribute causes the characters to have the top scan line of the character cell forced to foreground colour, including spaces. If background duration is set, then overline is set until the end of the text area. CC: The overline attribute (see Table 16, Serial Mode 0/1, bit 5) is valid from the time set until end of row or otherwise modified. Overlining of italic characters is not possible. TXT: This attribute is not available. 18.3.11 END OF ROW CC: The number of characters in a row is flexible and can be determined by the end of row attribute (see Table 16, Serial Mode 1, bit 9). However, the maximum number of character positions displayed is determined by the setting of the MMR Text Position Horizontal and MMR Text Area End. Note that when using the end of row attribute the next character location after the attribute should always be occupied by a `space'. TXT: This attribute is not available, row length is fixed at 40 characters. 18.3.12 FRINGING A fringe (shadow) can be defined around characters. The fringe direction is individually selectable in any of the North, South, East and West direction using the MMR Fringing Control. The colour of the fringe can also be defined as one of the entries in the CLUT, again using MMR Fringing Control. An example of south and south-west fringing is shown in Fig.18. CC: The fringe attribute (see Table 16, Serial Mode 0, bit 9) is valid from the time set until the end of the row or otherwise modified. TXT: The display of fringing in TXT mode is controlled by the TXT4.SHADOW ENABLE bit. When set, all the alphanumeric characters being displayed are shadowed, graphics characters are not shadowed. 18.3.13 MESHING The attribute effects the background colour being displayed. Alternate pixels are displayed as the background colour or video.The structure is offset by 1 pixel from scan line to scan line, thus achieving a checker board display of the background colour and video. An example of meshing is shown in Fig.19. CC: The setting of the MSH bit in MMR Display Control has the effect of meshing any background colour. TXT: There are two meshing attributes one that only affects black background colours TXT4.B MESH ENABLE and a second that only affects backgrounds other than black TXT4.C MESH ENABLE. A black background is defined as CLUT entry 8, a non-black background is defined as CLUT entry 9 to 15. 18.3.14 CURSOR The cursor operates by reversing the background and foreground colours in the character position pointed to by the active cursor position. The cursor is enabled using TXT7.CURSOR ON. When active, the row the cursor appears on is defined by TXT9.R<4:0> and the column is defined by TXT10.C<5:0>. The position of the cursor can be fixed using TXT9.CURSOR FREEZE. The cursor display is shown in Fig.20. CC: The valid range for row is 0 to 15. The valid range for column is 0 to 47. The cursor remains rectangular at all times, its shape is not affected by italic attribute, therefore it is not advised to use the cursor with italic characters. TXT: The valid range for row positioning is 0 to 24. The valid range for column is 0 to 39. 2000 Feb 23 47 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth MBK972 Fig.18 South and south-west fringing. handbook, full pagewidth MBK973 Fig.19 Meshing and Meshing/fringing (south + west). handbook, full pagewidth AB C D E F MBK971 Fig.20 Cursor display. 2000 Feb 23 48 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.3.15 SPECIAL GRAPHICS CHARACTERS CC/TXT: Several special characters are provided for improved OSD effects. These characters provide a choice of four colours within a character cell. The total number of special graphics characters is limited to 16. They are stored in the character codes 8XH and 9XH of the character table (32 ROM characters), or in the DRCs which overlay character codes 8XH and 9XH. Each special graphics character uses two consecutive normal characters. Fringing, underline and overline is not possible for special graphics characters. Special graphics characters are activated when TXT20.OSD PLANES = 1. SAA55xx Table 14 Special character colour allocation PLANE 1 0 0 1 1 PLANE 0 0 1 0 1 COLOUR ALLOCATION background colour foreground colour CLUT entry 6 CLUT entry 7 If the screen colour is transparent (implicit in mixed mode) and inside the object the box attribute is set, then the object is surrounded by video. If the box attribute is not set the background colour inside the object will also be displayed as transparent. handbook, full pagewidth background colour "set at" (Mode 0) serial attribute background colour "set after" (Mode 1) VOLUME background colour foreground colour 7 foreground colour normal character foreground colour 6 special character MGK550 This example could also be done with 8 special characters. Fig.21 Special character example. 2000 Feb 23 49 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.4 Character and attribute coding Table 15 Parallel character coding BITS 0 to 7 8 to 10 11 18.4.2 SAA55xx This section describes the character and attribute coding for each mode. 18.4.1 CC MODE DESCRIPTION 8 bit character code 3 bits for 8 foreground colours mode bit: 0 = Parallel code Character coding is split into character oriented attributes (parallel) and character group coding (serial). The serial attributes take effect either at the position of the attribute (set at), or at the following location (set after) and remain effective until either modified by a new serial attribute or until the end of the row. A serial attribute is represented as a space (the space character itself however is not used for this purpose), the attributes that are still active, e.g. overline and underline will be visible during the display of the space. The default setting at the start of a row is: * x1 size * Flash off * Overline off * Underline off * Italics off * Display mode = superimpose * Fringing off * Background colour duration = 0 * End of row = 0. The coding is done in 12-bit words. The codes are stored sequentially in the Display memory. A maximum of 768 character positions can be defined for a single display. TXT MODE Character coding is in a serial format, with only one attribute being changed at any single location. The serial attributes take effect either at the position of the attribute (set at), or at the following location (set after). The attribute remains effective until either modified by new serial attributes or until the end of the row. The default settings at the start of a row are: * Foreground colour white (CLUT address 7) * Background colour black (CLUT address 8) * Horizontal size x1, vertical size x1 (normal size) * Alphanumeric on * Contiguous mosaic graphics * Release mosaics * Flash off * Box off * Conceal off * Twist off. The attributes have individual codes which are defined in the basic character table (see Fig.22). 2000 Feb 23 50 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Table 16 Serial character coding DESCRIPTION BIT 0 to 3 4 SERIAL MODE 0 (SET AT) 4 bits for 16 background colours Underline switch: 0 = underline off 1 = underline on Overline switch: 0 = overline off 1 = overline on Display mode: 0 = superimpose 1 = boxing Flash switch: 0 = flash off 1 = flash on Italics switch 0 = italics off 1 = italics on Fringing switch: 0 = fringing off 1 = fringing on Switch for serial coding: 0 = mode 0 1 = mode 1 Mode bit: 1 = serial code SERIAL MODE 1 CHAR.POS. 1 (SET AT) 4 bits for 16 background colours Horizontal size: 0 = normal 1 = x2 Vertical size: 0 = normal 1 = x2 Display mode: 0 = superimpose 1 = boxing Foreground colour switch: 0 = Bank 0 (colours 0 to 7) 1 = Bank 1 (colours 8 to 15) Background colour duration: 0 = stop BGC 1 = set BGC to end of row End of row: 0 = continue row 1 = end row Switch for serial coding: 0 = mode 0 1 = mode 1 Mode bit: 1 = serial code SAA55xx CHAR.POS. >1 (SET AFTER) 4 bits for 16 background colours Underline switch: 0 = underline off 1 = underline on Overline switch: 0 = overline off 1 = overline on Display mode: 0 = superimpose 1 = boxing Foreground colour switch: 0 = Bank 0 (colours 0 to 7) 1 = Bank 1 (colours 8 to 15) Background colour duration (set at): 0 = stop BGC 1 = set BGC to end of row End of row (set at): 0 = continue row 1 = end row Switch for serial coding 0 = mode 0 1 = mode 1 Mode bit: 1 = serial code 5 6 7 8 9 10 11 2000 Feb 23 51 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 2000 Feb 23 52 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 nat opt OSD Philips Semiconductors E/W = 0 B I T S b7 b6 b5 b4 b3 b2 b1 b0 r o w 0 0 0 0 0 column 0 0 0 0 0 1 graphics black graphics red graphics green 0 0 0 1 2 0 0 1 0 2a 3 0 0 1 1 3a 4 nat opt 0 1 0 0 5 0 1 0 1 6 nat opt 0 1 1 0 6a 7 0 1 1 1 7a 8 1 0 0 0 8a 9 1 0 0 1 9a A 1 0 1 0 B background black back ground red background green background yellow background blue background magenta background cyan background white 1 0 1 1 C 1 1 0 0 D 1 1 0 1 E 1 1 1 0 F 1 1 1 1 D 1 1 0 1 E/W = 1 TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 1 1 1 0 E 1 1 1 1 F alpha black alpha red OSD OSD OSD OSD 0 0 0 1 1 OSD OSD OSD OSD 0 0 1 0 2 alpha green alpha yellow OSD OSD OSD OSD 0 0 1 1 3 graphics yellow nat opt OSD OSD OSD OSD 0 1 0 0 4 alpha blue alpha magenta graphics blue graphics magenta nat opt OSD OSD OSD OSD 0 1 0 1 5 OSD OSD OSD OSD 0 1 1 0 6 alpha cyan alpha white graphics cyan graphics white conceal display OSD OSD OSD OSD 0 1 1 1 7 OSD OSD OSD OSD 8 flash OSD OSD OSD OSD 9 steady contiguous graphics separated graphics OSD OSD OSD OSD A end box OSD OSD OSD OSD B start box twist nat opt nat opt OSD OSD OSD OSD normal size OSD double height OSD double width OSD double size OSD MBK974 C normal height double height black back ground new back ground hold graphics release graphics nat opt nat opt OSD OSD OSD OSD D nat opt nat opt nat opt nat opt OSD OSD OSD OSD E double width double size OSD OSD OSD OSD Preliminary specification F nat opt handbook, full pagewidth OSD OSD OSD OSD SAA55xx character dependent on the language of page, refer to National Option characters customer definable On-Screen Display character Fig.22 TXT basic character set (Pan-European). Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.5 Screen and global controls 18.5.3 DISPLAY MODES SAA55xx A number of attributes are available that affect the whole display region, and cannot be applied selectively to regions of the display. 18.5.1 TV SCAN LINES PER ROW CC: When attributes superimpose or boxing (see Table 16, Serial Mode 0/1, bit 6) are set, the resulting display depends on the setting of the following screen control mode bits in the MMR Display Control. TXT: The display mode is controlled by the bits in the TXT5 and TXT6 registers. There are three control functions - Text on, Background on and Picture on. Separate sets of bits are used inside and outside teletext boxes so that different display modes can be invoked. TXT6 is used if the newsflash (C5) or subtitle (C6) bits in row 25 of the basic page memory are set otherwise TXT5 is used. This allows the software to set up the type of display required on newsflash and subtitle pages (e.g. text inside boxes, TV picture outside) this will be invoked without any further software intervention when such a page is acquired. When teletext box control characters are present in the display page memory, the appropriate box control bit must be set, TXT7.BOX ON 0, TXT7.BOX ON 1 - 23 or TXT7.BOX ON 24. This allows the display mode to be different inside the teletext box compared to outside. These bits are present to allow boxes in certain areas of the screen to be disabled. The use of teletext boxes for OSD messages has been superseded in this device by the OSD box concept, but these bits remain to allow teletext boxes to be used, if required. The number of TV scan lines per field used for each display row can be defined, the value is independent of the character size being used. The number of lines can be either 10, 13 or 16 per display row. The number of TV scan lines per row is defined TXT21.DISP LINES<1:0>. A value of 9 lines per row can be achieved if the display is forced into 525-line display mode by TXT17.FORCE DISP<1:0>, or if the device is in 10 line mode and the automatic detection circuitry within display finds 525-line display syncs. 18.5.2 CHARACTER MATRIX (H X V) There are three different character matrices available, these are 12 x 10, 12 x 13 and 12 x 16. The selection is made using TXT21.CHAR SIZE<1:0> and is independent of the number of display lines per row. If the character matrix is less than the number of TV scan lines per row then the matrix is padded with blank lines. If the character matrix is greater than the number of TV scan lines then the character is truncated. Table 17 Display modes MOD 0 MOD 1 0 1 0 1 0 0 1 1 DISPLAY MODE Video Full Text DESCRIPTION Disables all display activities, sets the RGB to true black and VDS to video. Displays screen colour at all locations not covered by character foreground or background colour. The box attribute has no effect. Mixed Screen Colour Displays screen colour at all locations not covered by character foreground, within boxed areas or, background colour. Mixed Video Mixed Video mode displays video at all locations not covered by character foreground, within boxed areas or, background colour. Table 18 TXT display control bits PICTURE ON 0 0 0 1 1 1 18.5.4 SCREEN COLOUR 53 TEXT ON 0 1 1 0 1 1 BACKGROUND ON X 0 1 X 0 1 EFFECT Text mode, black screen Text mode, background always black Text mode Video mode Mixed text and TV mode Text mode, TV picture outside text area 2000 Feb 23 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Screen colour is displayed from 10.5 ms to 62.5 ms after the active edge of the HSYNC input and on TV lines 23 to 310 inclusive, for a 625-line display, and lines 17 to 260 inclusive for a 525-line display. CC: The screen colour is defined by the MMR Display Control and points to a location in the CLUT table. The screen colour covers the full video width. It is visible when the Full Text or Mixed Screen Colour mode is set and no foreground or background pixels are being displayed. TXT: The register bits TXT17.SCREEN COL<2:0> can be used to define a colour to be displayed in place of TV picture and the black background colour. If the bits are all set to zero, the screen colour is defined as `transparent' and TV picture and background colour are displayed as normal. Otherwise the bits define CLUT entries 9 to 15. 18.6 18.6.1 Text display controls TEXT DISPLAY CONFIGURATION (CC MODE) 9 to 0 18.6.2 DISPLAY MAP SAA55xx The display map allows a flexible allocation of data in the memory to individual rows. Sixteen words are provided in the display memory for this purpose. The lower 10 bits address the first word in the memory where the row data starts. This value is an offset in terms of 16-bit words from the start of Display memory (8000H). The most significant bit enables the display when not within the scroll (dynamic) area. The display map memory is fixed at the first 16 words in the Closed Caption display memory. Table 19 Display map bit allocation BIT 11 10 FUNCTION Text display enable, valid outside soft scroll area. 0 = disable; 1 = enable. This bit is reserved, should be set to logic 0. Pointer to row data. Two types of areas are possible. The one area is static and the other is dynamic. The dynamic area allows scrolling of a region to take place. The areas cannot cross each other. Only one scroll region is possible. 2000 Feb 23 54 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth Display memory 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Text area display possible ROW 0 1 2 3 4 10 11 3 4 9 10 11 12 13 14 15 display map entries Enable bit = 0 soft scrolling display possible display possible MBK966 display data Fig.23 Display map and data pointers. 2000 Feb 23 55 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.6.3 SOFT SCROLL ACTION SAA55xx The dynamic scroll region is defined by the MMR Scroll Area, MMR Scroll Range, MMR Top Scroll line and the MMR Status. The scroll area is enabled when the SCON bit is set in MMR Status. The position of the soft scroll area window is defined using the Soft Scroll Position (SSP<3:0>), and the height of the window is defined using the Soft Scroll Height (SSH<3:0>) both are in MMR Scroll Range. The rows that are scrolled through the window are defined using the Start Scroll Row (STS<3:0>) and the Stop Scroll Row (SPS<3:0>) both are in MMR Scroll Area. The soft scrolling function is done by modifying the Scroll Line (SCL<3:0>) in MMR Top Scroll Line. and the first scroll row value SCR<3:0> in the MMR Status. If the number of rows allocated to the scroll counter is larger than the defined visible scroll area, this allows parts of rows at the top and bottom to be displayed during the scroll function. The registers can be written throughout the field and the values are updated for display with the next field sync. Care should be taken that the register pairs are written to by the software in the same field. Only a region that contains only single height rows or only double height rows can be scrolled. TXT: The display is organised as a fixed size of 25 rows (0 to 24) of 40 columns (0 to 39), This is the standard size for teletext transmissions. The control data in row 25 is not displayed but is used to configure the display page correctly. handbook, full pagewidth soft scroll position pointer SSP<3:0> e.g. 6 soft scroll height SSH<3:0> e.g. 4 ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 usable for OSD display should not be used for OSD display start scroll row STS<3:0> e.g. 3 soft scrolling area should not be used for OSD display usable for OSD display start scroll row SPS<3:0> e.g. 11 MBK967 Fig.24 Soft scroll area. 2000 Feb 23 56 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth ROW 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 row0 0-63 lines row1 P01 NBC scroll area offset row2 row3 row4 row5 row6 row7 row8 Closed Captioning data row n Closed Captioning data row n+1 Closed Captioning data row n+2 Closed Captioning data row n+3 Closed Captioning data row n+4 row13 row14 visible area for scrolling MBK977 Fig.25 CC text areas. 2000 Feb 23 57 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx handbook, full pagewidth 0 Row 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0 control data 9 10 23 39 non-displayable data byte 10 reserved MBK968 Fig.26 TXT text area. 2000 Feb 23 58 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.7 Display positioning SAA55xx The display consists of the screen colour covering the whole screen and the text area that is placed within the visible screen area. The screen colour extends over a large vertical and horizontal range so that no offset is needed. The text area is offset in both directions relative to the vertical and horizontal sync pulses. handbook, full pagewidth horizontal sync screen colour offset = 8 s 6 lines offset text vertical offset SCREEN COLOUR AREA horizontal sync delay TEXT AREA vertical sync 0.25 character offset text area start text area end 56 s MGL150 Fig.27 Display area positioning. 2000 Feb 23 59 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.7.1 SCREEN COLOUR DISPLAY AREA SAA55xx This area is covered by the screen colour. The screen colour display area starts with a fixed offset of 8 s from the leading edge of the horizontal sync pulse in the horizontal direction. A vertical offset is not necessary. Table 20 Screen colour display area POSITION Horizontal Vertical 525-LINE Start at 8 s after leading edge of horizontal sync for 56 s. Line 9, Field 1 (321, Field 2) to leading edge of vertical sync (line numbering using 625 standard). TEXT DISPLAY AREA The width of the text area is defined in the MMR Text Area End Register by setting the end character value TAE<5:0>. This number determines where the background colour of the Text Area will end if set to extend to the end of the row. It will also terminate the character fetch process thus eliminating the necessity of a row end attribute. This entails however writing to all positions. The vertical offset is set in the MMR Text Position Vertical. The offset value VOL<5:0> is done in number of TV scan lines. Note that the Text Position Vertical Register should not be set to 00H as the Display Busy interrupt is not generated in these circumstances. 18.8 Character set 18.7.2 The text area can be defined to start with an offset in both the horizontal and vertical direction. Table 21 Text display area POSITION Horizontal DESCRIPTION Up to 48 full sized characters per row. Start position setting from 8 to 64 characters from the leading edge of horizontal sync. Fine adjustment in quarter characters. 256 lines (nominal 41 to 297). Start position setting from leading edge of vertical sync, legal values are 4 to 64 lines (line numbering using 625 standard). To facilitate the global nature of the device the character set has the ability to accommodate a large number of characters, which can be stored in different matrices. 18.8.1 CHARACTER MATRICES The character matrices that can be accommodated in both display modes are: (H x V x planes) 12 x 9 x 1, 12 x 10 x 1, 12 x 13 x 1, 12 x 16 x 1. These modes allow two colours per character position. In CC mode two additional character matrices are available to allow four colours per character. (H x V x planes) 12 x 13 x 2, 12 x 16 x 2. The characters are stored physically in ROM in a matrix of size either 12 x 10 or 12 x 16. Vertical The horizontal offset is set in the MMR Text Area Start. The offset is done in full width characters using TAS<5:0> and quarter characters using HOP<1:0> for fine setting. The values 00H to 08H for TAS<5:0> will result in a corrupted display. The value 09H should also be avoided in the MMR Text Area Start as corruption of the row 24 display can occur. Alternative values are C8H or 49H to overcome this problem. 2000 Feb 23 60 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.8.2 CHARACTER SET SELECTION SAA55xx Four character sets are available in the device. A set can consist of alphanumeric characters as required by the WST or US Closed Captioning, Customer definable On-Screen Display characters, and Special Graphic characters. CC: Only a single character set can be used for display and this is selected using the Basic Set selection TXT18.BS<1:0>. When selecting a character set in CC mode, the Twist Set selection TXT19.TS<1:0> should be set to the same value as TXT18.BS<1:0> for correct operation. TXT: Two character sets can be displayed at once. These are the basic G0 set or the alternative G0 set (Twist Set). The basic set is selected using TXT18.BS<1:0>. Table 22 Character set selection BS1/TS1 0 0 1 1 BS0/TS0 0 1 0 1 CHARACTER SET Set 0 Set 1 Set 2 Set 3 The alternative/twist character set is defined by TXT19.TS<1:0>. Since the alternative character set is an option it can be enabled or disabled using TXT19.TEN, and the language code that is defined for the alternative set is defined by TXT19.TC<2:0>. The National option table is selected using TXT18.NOT<3:0>. A maximum of 31 National option tables can be defined when combined with the EAST/WEST control bit located in register TXT4. An example of the character set selection and definitions is show in Table 22. An example of the National option reference table is shown in Table 23. Only a certain number of national options will be relevant for each of the Character sets. EXAMPLE LANGUAGE Latin Greek - Closed Caption Table 23 National option selection C12 0 0 0 0 1 1 1 1 C13 0 0 1 1 0 0 1 1 C14 0 1 0 1 0 1 0 1 NOT<3:0> = 0000 NOT<3:0> = 0001 NOT<3:0> = 0010 English German Swedish Italian French Spanish Czech - Polish German Swedish Italian French - Czech - English German Swedish Italian French Spanish Turkish - ... ... ... ... ... ... ... ... ... NOT<3:0> = 1110 Polish German Estonian Lettish Russian Serb-Croat Czech - 2000 Feb 23 61 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.9 ROM addressing SAA55xx Three ROMs are used to generate the correct pixel information. The first contains the National option look-up table, the second contains the Basic character look-up table and the third contains the Character pixel information. Although these are individual ROMs, since they do not need to be accessed simultaneously they are all combined into a single ROM unit. 2400H handbook, full pagewidth CHARACTER PIXEL DATA (71680 x 12-BIT) LOOK-UP SET 3 0800H 0600H 710 TEXT OR 430 TEXT + 176 CC LOOK-UP SET 2 0400H 0800H LOOK-UP BASIC + NATIONAL OPTION 2048 LOCATIONS 0000H MBK978 LOOK-UP SET 1 0200H LOOK-UP SET 0 0000H Fig.28 ROM organisation. 2000 Feb 23 62 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.9.1 CHARACTER TABLE SAA55xx CC: The character table is shown in Fig.29. TXT: One of the character set options (Pan-European: Latin) is shown in Fig.22. handbook, full pagewidth Character code columns (bits 4 to 7) 0 1 (R) 2 SP ! 3 0 1 2 3 4 5 6 7 8 9 4 @ A B C D E F G H I J K L M N O 5 P Q R S T U V W X Y Z [ e ] I o 6 u a b c d e f g h i j k l m n o N n n MBK976 7 p q r s t u v w x y z c 8 9 A B C D E F 0 1 2 Character code rows (bits 0 to 3) 3 4 5 6 7 8 9 A B C D E F 1/2 TM a " # $ % & ( ) a _ e a e i o u + , - . / : ; < = > ? Special characters in column 8 and 9 Additional table locations for normal characters Table locations for normal characters Fig.29 Closed Caption character table. 2000 Feb 23 63 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.10 Redefinable characters A number of Dynamically Redefinable Characters (DRCs) are available. These are mapped onto the normal character codes, and replace the predefined ROM value. There are 32 DRCs, the first 16 occupy the character codes 80H to 8FH, the second 16 occupy the locations 90H to 9FH. This allows for 32 DRCs or 16 Special DRCs. SAA55xx The remapping of the standard OSD to the DRCs is activated when the TXT20.DRCS ENABLE bit is set. The selection of Normal or Special OSD symbols is defined by the TXT20.OSD PLANES. Each character is stored in a matrix of 12 x 16 x 1 (V x H x planes), this allows for all possible character matrices to be defined within a single location. handbook, full pagewidth address (HEX) 8800 CHARACTER 0 881F 8820 CHARACTER 1 883F 8840 CHARACTER 2 885F character code 80H character 0 81H 82H A 12 bits 8BC0 CHARACTER 30 8BDF 8BE0 CHARACTER 31 8BFF 9FH 9EH address (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F MBK969 Fig.30 Organisation of DRC RAM. 2000 Feb 23 64 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 18.11 Display synchronization The horizontal and vertical synchronizing signals from the TV deflection are used as inputs. Both signals can be inverted before being delivered to the Phase Selector section. CC: The polarity is controlled using either VPOL or HPOL bits in the MMR Text Position Vertical. TXT: The TXT1.H POLARITY and TXT1.V POLARITY bits control the polarity. A line locked 12 MHz clock is derived from the 12 MHz free running oscillator by the Phase Selector. This line locked clock is used to clock the whole of the Display block. The horizontal and vertical sync signals are synchronized with the 12 MHz clock before being used in the display section. 18.12 Video/Data switch (Fast Blanking) polarity The polarity of the video/data (Fast Blanking) signal can be inverted. The polarity is set with the VDSPOL bit in the MMR RGB Brightness. Table 24 Fast blanking signal polarity VDSPOL 0 0 1 1 VDS 1 0 0 1 CONDITION RGB display Video display RGB display Video display Table 25 RGB brightness BRI3 TO BRI0 0000 ... 1111 18.15 Contrast reduction SAA55xx RGB BRIGHTNESS lowest value ... highest value CC: This feature is not available in CC mode. TXT: The COR bits in SFRs TXT5 and TXT6 control when the COR output of the device is activated (i.e. pulled LOW). This output is intended to act on the TV's display circuits to reduce contrast of the video when it is active. The result of contrast reduction is to improve the readability of the text in a mixed teletext and video display. The bits in the TXT5 and TXT6 SFRs allow the display to be set up so that, for example, the areas inside teletext boxes will be contrast reduced when a subtitle is being displayed but that the rest of the screen will be displayed as normal video. 19 MEMORY MAPPED REGISTERS (MMR) The memory mapped registers are used to control the display. The registers are mapped into the microcontroller MOVX address space, starting at address 87F0H and extending to 87FFH. Table 26 MMR address summary REGISTER NUMBER 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MEMORY ADDRESS 87F0H 87F1H 87F2H 87F3H 87F4H 87F5H 87F6H 87F7H 87F8H 87F9H 87FAH 87FBH 87FCH 87FDH 87FEH 87FFH FUNCTION Display Control Text Position Vertical Text Area Start Fringing Control Text Area End Scroll Area Scroll Range RGB Brightness Status reserved reserved reserved HSYNC Delay VSYNC Sync Delay Top Scroll Line Configuration 18.13 Video/data switch adjustment To take into account the delay between the RGB values and the VDS signal due to external buffering, the VDS signal can be moved in relation to the RGB signals. The VDS signal can be set to be either a clock cycle before or after the RGB signal, or coincident with the RGB signal. This is done using VDEL<2:0> in the MMR Configuration. 18.14 RGB brightness control A brightness control is provided to allow the RGB upper output voltage level to be modified. The nominal value is 1 V into a 150 resistor, but can be varied between 0.7 V and 1.2 V. The brightness is set in MMR RGB Brightness. 2000 Feb 23 65 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Table 27 MMR map ADD R/W 87F0 87F1 87F2 87F3 87F4 87F5 87F6 87F7 87F8 NAME 7 SRC3 VPOL HOP1 FRC3 - SSH3 SPS3 VDSPOL BUSY - - - - 6 SRC2 HPOL HOP0 FRC2 - SSH2 SPS2 - FIELD - HSD6 VSD6 - VDEL2 5 SRC1 VOL5 TAS5 FRC1 TAE5 SSH1 SPS1 - SCON SCON HSD5 VSD5 - VDEL1 4 SRC0 VOL4 TAS4 FRC0 TAE4 SSH0 SPS0 - FLR FLR HSD4 VSD4 - VDEL0 - VOL3 TAS3 FRDN TAE3 SSP3 STS3 BRI3 SCR3 SCR3 HSD3 VSD3 SCL3 TXT/V 3 2 MSH VOL2 TAS2 FRDE TAE2 SSP2 STS2 BRI2 SCR2 SCR2 HSD2 VSD2 SCL2 - 1 MOD1 VOL1 TAS1 FRDS TAE1 SSP1 STS1 BRI1 SCR1 SCR1 HSD1 VSD1 SCL1 - SAA55xx 0 MOD0 VOL0 TAS0 FRDW TAE0 SSP0 STS0 BRI0 SCR0 SCR0 HSD0 VSD0 SCL0 - RESET 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H 00H R/W Display Control R/W Text Position Vertical R/W Text Area Start R/W Fringing Control R/W Text Area End R/W Scroll Area R/W Scroll Range R/W RGB Brightness R W Status 87FC R/W HSYNC Delay 87FD R/W VSYNC Delay 87FE R/W Top Scroll Line 87FF R/W Configuration CC 2000 Feb 23 66 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Table 28 MMR bit definition REGISTER BIT Display Control SRC3 to SRC0 MSH MOD1 to MOD0 screen colour definition meshing all background colours (logic 1) 00 = Video 01 = Full Text 10 = Mixed Screen Colour 11 = Mixed Video Text Position Vertical VPOL HPOL VOL5 to VOL0 Text Area Start HOP1 to HOP0 TAS5 to TAS0 Fringing Control FRC3 to FRC0 FRDN FRDE FRDS FRDW Text Area End TAE5 to TAE0 Scroll Area SSH3 to SSH0 SSP3 to SSP0 Scroll Range SPS3 to SPS0 STS3 to STS0 RGB Brightness VDSPOL VDS polarity 0 = RGB (1), Video (0) 1 = RGB (0), Video (1) BRI3 to BRI0 RGB brightness control stop scroll row start scroll row soft scroll height soft scroll position text area end, in full characters fringing colour, value address of CLUT fringe in north direction (logic 1) fringe in east direction (logic 1) fringe in south direction (logic 1) fringe in west direction (logic 1) fine horizontal offset in quarter of characters text area start inverted input polarity (logic 1) inverted input polarity (logic 1) display start vertical offset from VSYNC (lines) FUNCTION SAA55xx 2000 Feb 23 67 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) REGISTER BIT Status read BUSY FIELD FLR SCR3 to SCR0 Status write SCON FLR SCR3 to SCR0 HSYNC Delay HSD6 to HSD0 VSYNC Delay VSD6 to VSD0 Top Scroll Line SCL3 to SCL0 Configuration CC VDEL2 to VDEL0 closed caption mode (logic 1) pixel delay between VDS and RGB output 000 = VDS switched to video, not active 001 = VDS active one pixel earlier then RGB 010 = VDS synchronous to RGB 100 = VDS active one pixel after RGB TXT/V BUSY signal switch; horizontal (logic 1) top line for scroll VSYNC delay in number of 8-bit 12 MHz clock cycles HSYNC delay, in full size characters scroll area enabled (logic 1) active flash region background colour only displayed (logic 1) first scroll row access to display memory could cause display problems (logic 1) even field (logic 1) active flash region background only displayed (logic 1) first scroll row FUNCTION SAA55xx 2000 Feb 23 68 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 20 LIMITING VALUES In accordance with Absolute Maximum Rating System (IEC 60134). SYMBOL VDDX VI VO IO IIOK Tamb Tstg Note PARAMETER supply voltage (all supplies) input voltage (any input) output voltage (any output) output current (each output) DC input or output diode current ambient temperature storage temperature note 1 note 1 CONDITIONS MIN. -0.5 -0.5 -0.5 - - -20 -55 +4.0 VDD + 0.5 or 4.1 VDD + 0.5 10 20 +70 +125 MAX. SAA55xx UNIT V V V mA mA C C 1. This maximum value refers to 5 V tolerant I/Os and may be 6 V maximum, but only when VDD is present. 21 CHARACTERISTICS VDD = 3.3 V 10%; VSS = 0 V; Tamb = -20 to +70 C; unless otherwise specified. SYMBOL Supplies VDDX IDDP IDDC IDDC(id) IDDC(pd) IDDC(stb) IDDA IDDA(id) IDDA(pd) IDDA(stb) any supply voltage (VDD to VSS) Periphery supply current core supply current Idle mode core supply current Power-down mode core supply current Standby mode core supply current analog supply current Idle mode analog supply current Power-down mode analog supply current Standby mode analog supply current note 1 3.0 1 - - - - - - - - 3.3 - 12 383 666 5.1 45 444 433 809 3.6 - 18 600 900 9 48 700 700 950 V mA mA A A mA mA A A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Digital inputs RESET VIL VIH Vhys ILI Rpd LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current equivalent pull-down resistance VI = 0 VI = VDD - 1.85 0.44 - 55.73 - - - - 70.71 1.00 - 0.58 0.17 92.45 V V V A k 2000 Feb 23 69 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SYMBOL HSYNC AND VSYNC VIL VIH Vhys ILI LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current VI = 0 to VDD - 1.80 0.40 - - - - - 0.96 - 0.56 0.00 PARAMETER CONDITIONS MIN. TYP. SAA55xx MAX. UNIT V V V A Digital outputs FRAME, VDS VOL VOH tr tf LOW-level output voltage HIGH-level output voltage output rise time output fall time IOL = 3 mA IOH = 3 mA 10% to 90%; CL = 70 pF 10% to 90%; CL = 70 pF IOL = 3 mA - 2.84 7.50 6.70 - - 8.85 7.97 0.13 - 10.90 10.00 V V ns ns COR (OPEN-DRAIN OUTPUT) VOL VOH VIL VIH ILI tf LOW-level output voltage - 2.84 - 0.00 VI = 0 to VDD 10% to 90%; CL = 70 pF 10% to 90%; CL = 70 pF - 7.20 4.90 - - - - - 8.64 7.34 0.14 - 0.00 5.50 0.12 11.10 9.40 V V V V A ns ns HIGH-level pull-up output voltage IOL = -3 mA; push-pull LOW-level input voltage HIGH-level input voltage input leakage current output rise time output fall time Digital input/outputs P0.0 TO P0.4, P0.7, P1.0 TO P1.1, P2.1 TO P2.7, P3.0 TO P3.7 VIL VIH Vhys ILI VOL VOH tr LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time VI = 0 to VDD IOL = 4 mA IOH = -4 mA push-pull 10% to 90%; CL = 70 pF push-pull 10% to 90%; CL = 70 pF - 1.78 0.41 - - 2.81 6.50 - - - - - - 8.47 0.98 - 0.55 0.01 0.18 5.50 10.70 V V V A V V ns tf output fall time 5.70 7.56 10.00 ns 2000 Feb 23 70 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SYMBOL P1.2, P1.3 AND P2.0 VIL VIH Vhys ILI VOL VOH tr LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage HIGH-level output voltage output rise time VI = 0 to VDD IOL = 4 mA IOH = -4 mA push-pull 10% to 90%; CL = 70 pF push-pull 10% to 90%; CL = 70 pF - 1.80 0.42 - - 2.81 7.00 - - - - - - 8.47 0.99 - 0.56 0.02 0.17 5.50 10.50 PARAMETER CONDITIONS MIN. TYP. SAA55xx MAX. UNIT V V V A V V ns tf output fall time 5.40 7.36 9.30 ns P0.5 AND P0.6 VIL VIH ILI Vhys VOL VOH tr LOW-level input voltage HIGH-level input voltage input leakage current hysteresis of Schmitt trigger input LOW-level output voltage HIGH-level output voltage output rise time IOL = 8 mA IOH = -8 mA push-pull 10% to 90%; CL = 70 pF push-pull 10% to 90%; CL = 70 pF VI = 0 to VDD - 1.82 - 0.42 - 2.76 7.40 - - - - - - 8.22 0.98 - 0.11 0.58 0.20 5.50 8.80 V V A V V V ns tf output fall time 4.20 4.57 5.20 ns P1.4 TO P1.7 (OPEN-DRAIN) VIL VIH Vhys ILI VOL tf LOW-level input voltage HIGH-level input voltage hysteresis voltage of Schmitt trigger input input leakage current LOW-level output voltage output fall time VI = 0 to VDD IOL = 8 mA 10% to 90%; CL = 70 pF - 1.99 0.49 - - 69.70 - - - - - 83.67 1.08 - 0.60 0.13 0.35 103.30 V V V A V ns Analog inputs CVBS0 AND CVBS1 Vsync Vvid(p-p) Zsource 2000 Feb 23 sync voltage amplitude video input voltage amplitude (peak-to-peak value) source impedance 71 0.1 0.7 0 0.3 1.0 - 0.6 1.4 250 V V Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SYMBOL VIH CI IREF Rgnd resistor to ground resistor tolerance 2% - 24 - PARAMETER HIGH-level input voltage input capacitance CONDITIONS - MIN. 3.0 - - TYP. 10 SAA55xx MAX. VDDA + 0.3 V UNIT pF k ADC0 TO ADC3 VIH CI VPE VIH HIGH-level input voltage - - 9.0 V HIGH-level input voltage input capacitance - - - - VDDA 10 V pF Analog outputs R, G AND B IOL IOH output current (Black Level) output current (maximum Intensity) output current (70% of full Intensity) Rload CL load resistor to VSSA load capacitance VDDA = 3.3 V VDDA = 3.3 V Intensity level code = 15 dec VDDA = 3.3 V Intensity level code = 0 dec resistor tolerance 5% -10 6.0 - 6.67 +10 7.3 A mA 4.2 4.7 5.1 mA - - 150 - - 15 pF Analog input/output SYNC_FILTER Csync Vsync storage capacitor to ground sync filter level voltage for nominal sync amplitude - 0.35 100 0.55 - 0.75 nF V Crystal oscillator XTALIN VIL VIH CI XTALOUT CO output capacitance - - 10 pF LOW-level input voltage HIGH-level input voltage input capacitance VSSA - - - - - - VDDA 10 V V pF 2000 Feb 23 72 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SYMBOL PARAMETER CONDITIONS - - Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C Tamb = 25 C - - - - -20 - - MIN. TYP. - 30 20 60 - note 5 +85 SAA55xx MAX. UNIT Crystal specification; notes 2 and 3 fxtal CL C1 Rr Cosc C0 Txtal Xj Xd Notes 1. Peripheral current is dependent on external components and voltage levels on I/Os. 2. Crystal order number 4322 143 05561. 3. If the 4322 143 05561 crystal is not used, then the formulae in the crystal specification should be used. Where CIO = 7 pF, the mean of the capacitances due to the chip at XTALIN and at XTALOUT. Cext is a value for the mean of the stray capacitances due to the external circuit at XTALIN and XTALOUT. The maximum value for the crystal holder capacitance is to ensure start-up - Cosc may need to be reduced from the initially selected value. 4. 5. C osc(typ) = 2C L - ( C IO - C ext ) 1 C 0(max) = 35 - -- ( C osc + C IO + C ext ) 2 nominal frequency crystal load capacitance crystal motional capacitance resonance resistance capacitors at XTALIN, XTALOUT crystal holder capacitance temperature range adjustment tolerance drift fundamental mode 12 - - - note 4 - +25 - - MHz pF fF pF pF C 50 x 10-6 100 x 10-6 2000 Feb 23 73 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) Table 29 I2C-bus characteristics SAA55xx FAST-MODE I2C-bus SYMBOL fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tr tf tSU;STO Cb Notes 1. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. 2. The maximum fHD;DAT has only to be met if the device does not stretch the LOW period tLOW of the SCL signal. 3. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. 4. Cb = total capacitance of one bus line in pF. SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock set up time for a repeated START condition data hold time; notes 1 and 2 data set up time; note 3 rise time of both SDA and SCL signals; note 4 fall time of both SDA and SCL signals; note 4 set up time for STOP condition capacitive load for each bus line PARAMETER MIN. 0 1.3 0.6 1.3 0.6 0.6 0 100 20 20 0.6 - - - - - - 0.9 - 300 300 - 400 MAX. 400 kHz s s s s s s ns ns ns s pF UNIT 2000 Feb 23 74 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 22 QUALITY AND RELIABILITY SAA55xx This device will meet Philips Semiconductors General Quality Specification for Business group "Consumer Integrated Circuits SNW-FQ-611-Part E". The principal requirements are shown in Tables 30 to 33. Table 30 Acceptance tests per lot TEST Mechanical Electrical cumulative target: <80 ppm cumulative target: <100 ppm REQUIREMENTS Table 31 Processability tests (by package family) TEST Solderability Mechanical Solder heat resistance 0/16 on all lots 0/15 on all lots 0/15 on all lots REQUIREMENTS Table 32 Reliability tests (by process family) TEST Operational life Humidity life Temperature cycling performance CONDITIONS 168 hours at Tj = 150 C temperature, humidity, bias 1000 hours, 85 C, 85% RH (or equivalent test) Tstg(min) to Tstg(max) REQUIREMENTS <1000 FPM at Tj = 150 C <2000 FPM <2000 FPM Table 33 Reliability tests (by device type) TEST ESD and latch-up CONDITIONS REQUIREMENTS ESD Human body model 100 pF, 1.5 kW 2000 V ESD Machine model 200 pF, 0 W 200 V latch-up 100 mA, 1.5 x VDD (absolute maximum) Notes to Tables 30 to 33 1. ppm = fraction of defective devices, in parts per million. 2. FPM = fraction of devices failing at test condition, in Failures Per Million. 3. FITS = Failures In Time Standard. 2000 Feb 23 75 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... dbook, full pagewidth 2000 Feb 23 76 23 APPLICATION INFORMATION Philips Semiconductors TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 40 V VDD A0 A1 A2 VDD VDD Vtune PH2369 VDD 47 F VDD VSS VSS VSS P2.0/TPWM 1 2 3 4 5 6 7 8 9 10 11 12 13 VDD 100 nF VSS VSS EEPROM PCF8582E RC SCL SDA VDD VSS 52 51 50 49 48 47 46 45 44 43 42 41 40 P1.5/SDA1 P1.4/SCL1 P1.7/SDA0 P1.6/SCL0 P1.3/T1 P1.2/INT0 P1.1/T0 P1.0/INT1 VDDP RESET XTALOUT XTALIN OSCGND VDDC VSSP VSYNC HSYNC VDS R G B VDDA P3.4/PWM7 COR VPE FRAME VSS VSS VDD 150 to TV's display circuits VSS VDD 12 MHz 56 pF 100 nF VDD 47 F VSS field flyback line flyback VDD 10 F VDD IR RECEIVER TV control signals brightness contrast saturation hue volume (L) volume (R) VSS VAFC AV status P2.1/PWM0 P2.2/PWM1 P2.3/PWM2 P2.4/PWM3 P2.5/PWM4 P2.6/PWM5 P2.7/PWM6 P3.0/ADC0 P3.1/ADC1 P3.2/ADC2 P3.3/ADC3 program+ VSS program- VHF-L VHF-H menu TV control signals UHF VSSC P0.0 P0.1 P0.2 P0.3 P0.4 SAA55xx 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 minus(-) P0.5 plus(+) VSS VDD 1 k 1 k VSSA VSS 100 nF CVBS (IF) CVBS (SCART) 100 nF VSS 100 nF CVBS0 CVBS1 SYNC_FILTER IREF 24 k P0.6 P0.7 VDD Preliminary specification SAA55xx MBK980 Fig.31 Application diagram. Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 24 ELECTROMAGNETIC COMPATIBILITY (EMC) GUIDELINES Optimization of circuit return paths and minimisation of common mode emission will be assisted by using a double sided printed-circuit board (PCB) with low inductance ground plane. On a single-sided PCB a local ground plane under the whole Integrated Circuit (IC) should be present as shown in Fig.32. This should be connected by the widest possible connection back to the PCB ground connection, and bulk electrolytic decoupling capacitor. It should preferably not connect to other grounds on the way, and no wire links should be present in this connect. The use of wire links increases ground bounce by introducing inductance into the ground. The supply pins can be decoupled at the pin to the ground plane under the IC. This is easily accomplished using surface mount capacitors, which are more effective than leaded components at high frequency. SAA55xx Using a device socket will unfortunately add to the area and inductance of the external bypass loop. A ferrite bead or inductor with resistive characteristics at high frequencies may be utilised in the supply line close to the decoupling capacitor to provide a high impedance. To prevent pollution by conduction onto the signal lines (which may then radiate) signals connected to the VDD supply via a pull up resistor should not be connected to the IC side of this ferrite component. OSCGND should be connected only to the crystal load capacitors and not the local or circuit ground. Physical connection distances to associated active devices should be short. Output traces should be routed with close proximity to mutually coupled ground return paths. handbook, full pagewidth GND +3.3 V electrolytic decoupling capacitor (2 F) other GND connections VDDC VDDP VDDA VSSP ferrite beads SM decoupling capacitors (10 to 100 nF) under-IC GND plane GND connection note: no wire links under-IC GND plane VSSC VSSA IC MBK979 Fig.32 Power supply connections for EMC. 2000 Feb 23 77 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 25 PACKAGE OUTLINES SDIP52: plastic shrink dual in-line package; 52 leads (600 mil) SAA55xx SOT247-1 seating plane D ME A2 A L A1 c Z e b1 wM (e 1) MH b 52 27 pin 1 index E 1 26 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT247-1 REFERENCES IEC JEDEC MS-020 EIAJ EUROPEAN PROJECTION A max. 5.08 A1 min. 0.51 A2 max. 4.0 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 47.9 47.1 E (1) 14.0 13.7 e 1.778 e1 15.24 L 3.2 2.8 ME 15.80 15.24 MH 17.15 15.90 w 0.18 Z (1) max. 1.73 ISSUE DATE 95-03-11 99-12-27 2000 Feb 23 78 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) SAA55xx LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1 c y X 75 76 51 50 ZE A e E HE wM bp L pin 1 index 100 1 ZD bp D HD wM B vM B 25 vM A 26 detail X Lp A A2 (A 3) A1 e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1.0 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7 0o o 16.25 16.25 15.75 15.75 ISSUE DATE 00-01-19 00-02-01 2000 Feb 23 79 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 26 SOLDERING 26.1 Introduction to soldering through-hole mount packages SAA55xx The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. 26.3 Manual soldering This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. 26.2 Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. 26.4 Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING WAVE suitable(1) DBS, DIP, HDIP, SDIP, SIL Note suitable 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 2000 Feb 23 80 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) 27 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values SAA55xx This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 28 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 29 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2000 Feb 23 81 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) NOTES SAA55xx 2000 Feb 23 82 Philips Semiconductors Preliminary specification TV microcontrollers with Closed Captioning (CC) and On-Screen Display (OSD) NOTES SAA55xx 2000 Feb 23 83 Philips Semiconductors - a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI), Tel. +39 039 203 6838, Fax +39 039 203 6800 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW, Tel. +48 22 5710 000, Fax. +48 22 5710 001 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 58088 Newville 2114, Tel. +27 11 471 5401, Fax. +27 11 471 5398 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye, ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 3341 299, Fax.+381 11 3342 553 For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 2000 Internet: http://www.semiconductors.philips.com SCA 69 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753504/02/pp84 Date of release: 2000 Feb 23 Document order number: 9397 750 06788 |
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